Errata Sheet Rel. 1.5, 2018-07 Device XMC4500 Marking/Step ES-AC, AC Package PG-LQFP-100/144, PG-LFBGA-144 Overview Document ID is 081/18. This “Errata Sheet” describes product deviations with respect to the user documentation listed below. Table1 Current User Documentation Document Version Date XMC4500 Reference Manual V1.6 July 2016 XMC4500 Data Sheet V1.4 January 2016 Make sure that you always use the latest documentation for this device listed in category “Documents” at http://www.infineon.com/xmc4000. Notes 1. The errata described in this sheet apply to all temperature and frequency versions and to all memory size and configuration variants of affected devices, unless explicitly noted otherwise. 2. Devices marked with EES or ES are engineering samples which may not be completely tested in all functional and electrical characteristics, therefore they must be used for evaluation only. Specific test conditions for EES and ES are documented in a separate “Status Sheet”, delivered with the device. 3. XMC4000 devices are equipped with an ARM® Cortex®-M4 core. Some of the errata have a workaround which may be supported by some compiler tools. In order to make use of the workaround the corresponding compiler switches may need to be set. XMC4500, ES-AC, AC 1/102 Rel. 1.5, 2018-07 Subject to Agreement on the Use of Product Information Errata Sheet Conventions used in this Document Each erratum is identified by Module_Marker.TypeNumber: • Module: Subsystem, peripheral, or function affected by the erratum. • Marker: Used only by Infineon internal. • Type: type of deviation – (none): Functional Deviation – P: Parametric Deviation – H: Application Hint – D: Documentation Update • Number: Ascending sequential number. As this sequence is used over several derivatives, including already solved deviations, gaps inside this enumeration can occur. XMC4500, ES-AC, AC 2/102 Rel. 1.5, 2018-07 Subject to Agreement on the Use of Product Information Errata Sheet History List / Change Summary 1 History List / Change Summary Table2 History List Version Date Remark 1.0 2013-08 Initial AC step version. Previous step is AB. Changes wrt. XMC4500 AB Errata Sheet v1.2: Added ADC_AI.008, CCU8_AI.004, CPU_CM.004, DAC_CM.P001, ADC_AI.H003 1.1 2014-03 Added: ADC_TC.064, DSD_AI.001, SCU_CM.015, USB_CM.003, USIC_AI.020, ADC_AI.H008, ADC_TC.H011 Updated: ADC_AI.008, USIC_AI.008, RESET_CM.H001 1.2 2016-05 Added: ADC_AI.016, CACHE_CM.001, CCU8_AI.006, CCU_AI.006, DSD_AI.002, DTS_CM.001, ETH_CM.002, FCE_CM.001, PARITY_CM.001, PARITY_CM.002, PBA_CM.001, PORTS_CM.007, SCU_CM.021, SDMMC_CM.003, SDMMC_CM.004, SDMMC_CM.005, SDMMC_CM.006, SDMMC_CM.007, SDMMC_CM.008, SDMMC_CM.009, USB_CM.004, WDT_CM.001, POWER_CM.P002, POWER_CM.P004, ETH_AI.H001, USIC_AI.H004. Updated: SCU_CM.002. 1.3 2016-10 Added Functional Deviation: ADC_CM.001, CCU_AI.008, EBU_CM.001, USB_CM.005 Added Application Hint: MultiCAN_AI.H009 Added Application Documentation Update: WDT_CM.D001 XMC4500, ES-AC, AC 3/102 Rel. 1.5, 2018-07 Subject to Agreement on the Use of Product Information Errata Sheet History List / Change Summary Table2 History List (cont’d) Version Date Remark 1.4 2017-08 This Document. Added Functional Deviation: ACD_CM.002 For changes see column "Chg" in the tables below. 1.5 2018-07 This document. Added Functional Deviations: CPU_CM.005 Updated Functional Deviations: PORTS_CM.001 Added Application Hints: PORTS_CM.H002 Added Documentation Updates: MPU_CM.D001, STARTUP_CM.D003 For updates and new issues see column "Chg" in the tables below. Table3 Errata fixed in this step Errata Short Description Change ADC_AI.002 Result of Injected Conversion may be wrong Fixed CCU8_AI.002 CC82 Timer of the CCU8x module cannot Fixed use the external shadow transfer trigger connected to the POSIFx module PMU_CM.001 Branch from non-cacheable to cacheable Fixed address space instruction may corrupt the program execution PORTS_CM.002 P0.9 Pull-up permanently active Fixed STARTUP_CM.001 CAN Bootstrap Loader Fixed XMC4500, ES-AC, AC 4/102 Rel. 1.5, 2018-07 Subject to Agreement on the Use of Product Information Errata Sheet History List / Change Summary Table4 Functional Deviations Functional Short Description Chg Pg Deviation ADC_AI.008 Wait-for-Read condition for register 13 GLOBRES not detected in continuous auto-scan sequence ADC_AI.016 No Channel Interrupt in Fast Compare 14 Mode with GLOBRES ADC_CM.001 Conversion results can be wrong if groups 14 are not synchronized ADC_CM.002 Converter diagnostics not functional 16 ADC_TC.064 Effect of conversions in 10-bit fast 17 compare mode on post-calibration CACHE_CM.001 Instruction buffer invalidation control bit 18 needs to be cleared after an invalidation was triggered CCU4_AI.001 CCU4 period interrupt is not generated in 18 capture mode CCU8_AI.001 CCU8 Floating Prescaler function does not 21 work with Capture Trigger 1 CCU8_AI.003 CCU8 Parity Checker Interrupt Status is 22 cleared automatically by hardware CCU8_AI.004 CCU8 output PWM glitch when using low 24 side modulation via the Multi Channel Mode CCU8_AI.006 Timer concatenation does not work when 27 using external count signal CCU_AI.001 CCU4 and CCU8 capture full flags do not 29 work when module clock is faster than peripheral bus clock XMC4500, ES-AC, AC 5/102 Rel. 1.5, 2018-07 Subject to Agreement on the Use of Product Information Errata Sheet History List / Change Summary Table4 Functional Deviations (cont’d) Functional Short Description Chg Pg Deviation CCU_AI.002 CCU4 and CCU8 Prescaler 31 synchronization clear does not work when Module Clock is faster than Peripheral Bus Clock CCU_AI.003 CCU4 and CCU8 capture full flag is not 32 cleared if a capture event occurs during a bus read phase CCU_AI.004 CCU4 and CCU8 Extended Read Back loss 35 of data CCU_AI.005 CCU4 and CCU8 External IP clock Usage 37 CCU_AI.006 Value update not usable in period dither 38 mode CCU_AI.008 Clock ratio limitation when using MCSS 39 inputs CPU_CM.001 Interrupted loads to SP can cause 40 erroneous behavior CPU_CM.004 VDIV or VSQRT instructions might not 41 complete correctly when very short ISRs are used CPU_CM.005 Store immediate overlapping exception New 42 return operation might vector to incorrect interrupt DAC_CM.001 DAC immediate register read following a 44 write issue DAC_CM.002 No error response for write access to read 44 only DAC ID register DEBUG_CM.001 OCDS logic in peripherals affected by 44 TRST DEBUG_CM.002 CoreSight logic only reset after power-on 45 reset XMC4500, ES-AC, AC 6/102 Rel. 1.5, 2018-07 Subject to Agreement on the Use of Product Information Errata Sheet History List / Change Summary Table4 Functional Deviations (cont’d) Functional Short Description Chg Pg Deviation DSD_AI.001 Possible Result Overflow with Certain 45 Decimation Factors DSD_AI.002 Timestamp can be calculated wrong 46 DTS_CM.001 DTS offset calibration value limitations 48 EBU_CM.001 32-bit memory with byte write capability 49 needs address ranges 0 and 1 enabled ETH_AI.001 Incorrect IP Payload Checksum at 50 incorrect location for IPv6 packets with Authentication extension header ETH_AI.002 Incorrect IP Payload Checksum Error 51 status when IPv6 packet with Authentication extension header is received ETH_AI.003 Overflow Status bits of Missed Frame and 52 Buffer Overflow counters get cleared without a Read operation ETH_CM.002 MAC provides incorrect status and 53 corrupts frames when RxFIFO overflow occurs on penultimate word of Rx frames of specific lengths FCE_CM.001 Result value is wrong if read directly after 54 last write GPDMA_CM.001 Unexpected Block Complete Interrupt 54 During Multi-Block Transfers GPDMA_CM.002 GPDMA doesn't Accept Transfer During/In 56 2nd Cycle of 2-Cycle ERROR Response LEDTS_AI.001 Delay in the update of FNCTL.PADT bit 57 field PARITY_CM.001 Parity error signaling can be suppressed 61 in write/read sequence XMC4500, ES-AC, AC 7/102 Rel. 1.5, 2018-07 Subject to Agreement on the Use of Product Information Errata Sheet History List / Change Summary Table4 Functional Deviations (cont’d) Functional Short Description Chg Pg Deviation PARITY_CM.002 Clock limitations for ETH and SDMMC 62 modules when using parity check of module SRAMs PBA_CM.001 Bus error request suppressed in 63 sequential write to peripheral bridge PORTS_CM.001 P15_PDISC.[4,5] register bits cannot be Upd 64 written ate PORTS_CM.005 Different PORT register reset values after 64 module reset PORTS_CM.007 P14 and P15 cannot be used in boundary 65 scan test POSIF_AI.001 Input Index signal from Rotary Encoder is 65 not decoded when the length is 1/4 of the tick period RTC_CM.001 RTC event might get lost 68 SCU_CM.002 Missed wake-up event during entering 68 external hibernate mode SCU_CM.003 The state of HDCR.HIB bit of HCU gets 69 updated only once in the register mirror after reset release SCU_CM.006 Deep sleep entry with PLL power-down 69 option generates SOSCWDGT and SVCOLCKT trap SCU_CM.015 Functionality of parity memory test 70 function limited SCU_CM.021 Registering of service requests in SRRAW 71 register can fail SDMMC_CM.001 Unexpected interrupts after execution of 72 CMD13 during bus test XMC4500, ES-AC, AC 8/102 Rel. 1.5, 2018-07 Subject to Agreement on the Use of Product Information Errata Sheet History List / Change Summary Table4 Functional Deviations (cont’d) Functional Short Description Chg Pg Deviation SDMMC_CM.002 Unexpected Tx complete interrupt during 72 R1b response SDMMC_CM.003 SDMMC input pins cannot be released for 73 other usage SDMMC_CM.004 Busy response from card in write resume 74 operation not detected SDMMC_CM.005 Controller sends other command when 74 Auto CMD12 enabled SDMMC_CM.006 Stream write issue due to wrong FIFO 75 handling causes data corruption in eMMC mode SDMMC_CM.007 Consecutive write to the same register in 75 SD clock domain SDMMC_CM.008 Receive state machine hangs if driver 76 programs stop at block gap request using CMD18 when receive buffers are full SDMMC_CM.009 Latching current value in the response 76 register USB_CM.002 GAHBCFG.GlblIntrMsk not cleared with a 77 software reset USB_CM.003 Endpoint NAK not sent in Device Class 77 applications with multiple endpoints enabled USB_CM.004 USB core is not able to detect resume or 78 new session request after PHY clock is stopped USB_CM.005 DMA support for USB host mode operation 79 USIC_AI.005 Only 7 data bits are generated in IIC mode 79 when TBUF is loaded in SDA hold time USIC_AI.006 Dual SPI format not supported 80 XMC4500, ES-AC, AC 9/102 Rel. 1.5, 2018-07 Subject to Agreement on the Use of Product Information Errata Sheet History List / Change Summary Table4 Functional Deviations (cont’d) Functional Short Description Chg Pg Deviation USIC_AI.007 Protocol-related argument and error bits in 80 register RBUFSR contain incorrect values following a received data word USIC_AI.008 SSC delay compensation feature cannot 82 be used USIC_AI.009 Baud rate generator interrupt cannot be 82 used USIC_AI.010 Minimum and maximum supported word 83 and frame length in multi-IO SSC modes USIC_AI.011 Write to TBUF01 has no effect 83 USIC_AI.013 SCTR register bit fields DSM and HPCDIR 84 are not shadowed with start of data word transfer USIC_AI.014 No serial transfer possible while running 84 capture mode timer USIC_AI.015 Wrong generation of FIFO standard 84 transmit/receive buffer events when TBCTR.STBTEN/RBCTR.SRBTEN = 1 USIC_AI.016 Transmit parameters are updated during 85 FIFO buffer bypass USIC_AI.018 Clearing PSR.MSLS bit immediately 86 deasserts the SELOx output signal USIC_AI.020 Handling unused DOUT lines in multi-IO 86 SSC mode WDT_CM.001 No overflow is generated for WUB default 87 value XMC4500, ES-AC, AC 10/102 Rel. 1.5, 2018-07 Subject to Agreement on the Use of Product Information