Shichun Qu · Yong Liu Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor Applications Wafer-Level Chip-Scale Packaging ThiSisaFMBlankPage Shichun Qu (cid:129) Yong Liu Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor Applications ShichunQu YongLiu FairchildSemiconductor FairchildSemiconductor SanJose,California SouthPortland,Maine USA USA ISBN978-1-4939-1555-2 ISBN978-1-4939-1556-9(eBook) DOI10.1007/978-1-4939-1556-9 SpringerNewYorkHeidelbergDordrechtLondon LibraryofCongressControlNumber:2014946821 #SpringerScience+BusinessMediaNewYork2015 Thisworkissubjecttocopyright.AllrightsarereservedbythePublisher,whetherthewholeorpart of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation,broadcasting,reproductiononmicrofilmsorinanyotherphysicalway,andtransmissionor informationstorageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilar methodologynowknownorhereafterdeveloped.Exemptedfromthislegalreservationarebriefexcerpts inconnectionwithreviewsorscholarlyanalysisormaterialsuppliedspecificallyforthepurposeofbeing enteredandexecutedonacomputersystem,forexclusiveusebythepurchaserofthework.Duplication ofthispublicationorpartsthereofispermittedonlyundertheprovisionsoftheCopyrightLawofthe Publisher’s location, in its current version, and permission for use must always be obtained from Springer.PermissionsforusemaybeobtainedthroughRightsLinkattheCopyrightClearanceCenter. ViolationsareliabletoprosecutionundertherespectiveCopyrightLaw. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publicationdoesnotimply,evenintheabsenceofaspecificstatement,thatsuchnamesareexempt fromtherelevantprotectivelawsandregulationsandthereforefreeforgeneraluse. While the advice and information in this book are believed to be true and accurate at the date of publication,neithertheauthorsnortheeditorsnorthepublishercanacceptanylegalresponsibilityfor anyerrorsoromissionsthatmaybemade.Thepublishermakesnowarranty,expressorimplied,with respecttothematerialcontainedherein. Printedonacid-freepaper SpringerispartofSpringerScience+BusinessMedia(www.springer.com) Preface A wafer-level chip-scale package (WLCSP) is a bare die package that offers not only the smallest possible footprints in all IC package forms, but also superior electrical and thermal performance, mostly credited to the direct solder intercon- nections that are low in electrical and thermal resistance and low in inductance betweenchipandapplicationPCBitisassembledon.Formobileelectronics,where performanceneedstobehighandsizemustbesmall,heatdissipationislimitedto the conduction through PCB tothe case of the mobiledevice; WLCSP is the best chippackageoptionthatbalancestheseeminglyconflictingrequirements. Sharing the same root with the flip chip package, WLCSP took a bold step forward by placing sufficient size solder bumps on a semiconductor chip and allowing ittobeflipmounted directly onanapplication board. With solder joints takingupasignificantportionofchip/PCBCTEmismatchingthermal/mechanical stresses,WLCSPhasprovedtobereliableinmobile-specificreliabilitytests,such as droptest, bending test, and temperature cycling tests, besides the basic device- specificreliabilitytests.Therobustnessofthispackagingformisalsodemonstrated withlastinglifeofeverydayuseonbillionsofmobileconsumerelectronicsdevices. With continuous evolvement in the bumping technologies, such as polymer re-passivated bump on pad (BoP), copper redistribution layer (RDL), front side moldedcopperpostontheRDL,aggressivesiliconbackgrinding,advancedsolder alloys,anddesignknow-how,WLCSPhasexpandedthesizerangefromearlydays under2–3mmto8–10mmsiliconchipsize, whileatthesametimecontinuously reducingtheperunitcostwithscalingfactorsofhighvolumeproductionin200and 300 mm wafer sizes. The availability of package size range and favorable cost structuremakesWLCSPagoodpackagingcandidateforawidearrayofsemicon- ductordevices,fromanalog/mixedsignalandwirelessconnectivitychipstoopto- electronics,powerelectronics,andlogicandmemorychips.Innovationsinwafer- level3DchipstackingfurtherenableWLCSPaviableoptionforMEMSandsensor chippackaging. ThebeautyofWLCSPisthestart-to-finishwafer-basedprocessing.Itblursthe line between semiconductor wafer fab processes and the backend packaging operations. There is no singulated die packaging operation typically seen in all othertypesofchippackagingoperations.WLCSPpackagingoperations,including bumping, inspections, and tests, are fully automated from cassette to cassette, v vi Preface which is known for high efficiency. Also benefiting from half a century of wafer processingknow-howistheoverallWLCSPpackaging(oftenreferredasbumping) yield,whichisquitecloseto100%.Withthisinmind,itisnotasurpriseatalltosee even for die fan-out packages, wafer form processing, based on the reconstituted wafersin200or300mmsize,isthepreferredapproachfromstart. WLCSPhasappreciatedenormousgrowthinthepastdecade,largelybecauseof globalconsumerdemandformobilecommunicationandcomputingdevices.With double-digitmarketvalue(waferbumping,test,anddieprocessingserviceinclud- ingbackgrind,marking,saw,andtapeandreel)growthstillinsight,WLCSPisone of the most important packaging technologies for packaging engineers of all backgrounds. Itisthepurposeofthisbooktoprovidereadersacomprehensiveoverviewofthe general WLCSP packaging technology. It is also the intention of the authors to share specific knowledge of WLCSP in analog and power semiconductors. Advanced WLCSP technologies, such as 3D wafer-level stacking, TSV, MEMS, andopto-electronicsapplications,arealsobrieflyintroducedinthisbook. The book consists of ten chapters, with an overview of the demand and challenges for analog and power WLCSP in Chap. 1; Chaps. 2 and 3 cover the basic concepts of fan-in and fan-out WLCSP, bumping process flow, design considerations,andreliabilityassessment.Chapter4isdesignatedforthestackable packaging solutions involving WLCSP. Chapter 5 gets into the details of wafer- leveldiscretepowerMOSFETpackagedesignconsiderations.Chapter6discusses more on TSV/stack die WLCSP for the integration of analog and power solution. Chapter7isallonthecriticaltopicsofthermalmanagement,design,andanalysis forWLCSP.Chapter8continuesontheelectricalandmultiplephysicssimulation foranalogandpowerWLCSP,withthenewprogressonelectromigratonstudyof 0.18μmpowertechnology.Chapter9touchesontheassemblyofWLCSPdevices. Chapter 10 wraps up the book with reliability and general testing of WLCSP semiconductors. Comingupwithyearsofexperienceinsemiconductorpackaging,andwithfocus onwafer-level packaging, theauthors attemptedtoprovide well-balancedand yet up-to-datecontentintenchapters.Wewishthisbookisagoodstartingmaterialfor youngengineerswhoneedtolearnthemostimportantofWLCSPtechnologyina shorttime.Atthe same time,we alsohopethat seasoned engineersfind thisbook good references for them to not only keep up with the rapid technology advance- ment,butalsotohelpaddressdailyengineeringchallenges. SanJose,CA,USA ShichunQu SouthPortland,ME,USA YongLiu Acknowledgments The book is impossible without the dedication of Merry Stuber, editor from Springer for timely reminder and coordination of draft submission and critical reviews. Doug Dolan from Fairchild Semiconductor deserves special thanks for taking time performing the primary legal review of all ten chapters. The authors would also like tothankFairchild Semiconductorfor general supportof technical publications that led directly to the completion of this book. A few names are mentionedhereforthesupportovertheyears,SureshBelani,directorforpackag- ing, OS Jeon, senior director for packaging, Dan Kinzer, former chief technology officer, and Paul Hughes, general consults, all from Fairchild. Many coworkers contributedtothedataquotedinthisbookandtheauthorliketotakethisopportu- nity to express our sincere thanks as well: Mr. Richard Qian, Mr. Zhongfa Yuan, and Dr. Yumin Liu for simulation support; Dr. Qi Wang for wafer-level power MOSFETandprocess;Dr.JunCai(formerDeviceandProcessSeniorMemberof Technical Staff ) and Mr. Andrew Schoenberger (former Fairchild wafer-level process engineer) for the WLCSP ball shearing test; Dr. Yangjian Xu, Mr. Ye Zhang,andHuixianWu(ZhejiangUniversityofTechnology)fortheWLCSPball shearing test and stacking simulations; Dr. Jifa Hao for the wafer-level electromigration test of 0.18 μm power interconnects; Dr. Yuanxiang Zhang (Quzhou University) for building the wafer-level electromigration model; Ms.JiaminNiandProfessorAntoinetteManiatty(RensselaerPolytechnicInstitute ) for solder joint electromigration; Etan Schaham for inspiring discussions of WLCSP packaging challenges; Rob Travis and Dennis Tummy for insights of devicereliabilityandfabprocessinteractions;Mr.DougHawks(formerFairchild packagingengineer)forMCSPdevelopment;Mr.WilliamNewberryforelectrical simulationmethodology;JihwanKimfortheWLCSPdroptest;andSteveMartin for support for routine WLCSP research and development activities. Several organizations within Fairchild are also mentioned here for the support WLCSP assemblyandtests:FairchildBucheonsiteandFairchildCebusite. Muchofthematerialinthisbookwasderivedfrompreviouspapersandresearch notes by the authors. Here the authors like to thank several professional societies thatpublishedsomeofthismaterialandallowedtoreproducesomecontentsinthis vii viii Acknowledgments book. They are the Institute of Electrical and Electronic Engineers (IEEE) and its Conferences, Proceedings, and Journals, including IEEE Transactions on Components and Packaging Technology and IEEE Transactions on Electronics Packaging Manufacturing. The authors also appreciate the following Conferences forallowingthereorganizationandreproductionofpreviouslypublishedmaterials: IEEE Electronic Components and Technology Conference (ECTC), IEEE International Conference on Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), and IEEE International Conference on Thermal, Mechanical and Mult-Physics Simulation and Experiments in Microelectronics andMicrosystems(EuroSimE). Lastly, but most importantly, the authors would like to thank their perspective families for the support that made it possible to spend numerous weekends and nights onthisbook.ShichunQulikestothankhiswife ShanHuanganddaughter Claire Qu, and Yong Liu likes to express his appreciation to his wife, Jane Chen, andsonsJunyangLiuandAlexanderLiufortheirgreatloveandpatiencethrough- outthe2+yearsofwritingthisbook. SanJose,CA,USA ShichunQu SouthPortland,ME,USA YongLiu Contents 1 DemandandChallengesforWafer-LevelChip-ScaleAnalog andPowerPackaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 DemandforAnalogandPowerWLCSP. .. . . .. . . .. . .. . . .. 1 1.2 ImpactofDieShrinkage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.1 DieShrinkageImpact. . . . . . . . .. . . . . . . . . . . . . . . . 2 1.2.2 Wafer-LevelSystemonChipVersusSystem inPackage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Fan-InVersusFan-Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 PowerWLCSPDevelopment. . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4.1 Wafer-LevelMosfetComparedtoRegular DiscretePowerPackage. . . . . . . . . . . . . . . . . . . . . . . 5 1.4.2 HigherCurrentCarryingCapability. . . . . . . . . . . . . . 7 1.4.3 LowRds(on)ResistanceandBetterThermal Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4.4 TrendsinPowerICPackages. . . . . . . . . . . . . . . . . . . 8 1.4.5 TrendsinWafer-LevelPassives. . . . . . . . . . . . . . . . . 10 1.4.6 Wafer-LevelStack/3DPowerDieSIP. . . . . . . . . . . . . 11 1.5 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Fan-InWafer-LevelChip-ScalePackage. . . . . . . . . . . . . . . . . . . . 15 2.1 IntroductionofFan-InWLCSP. . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 WLCSPBumpingTechnology. . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 WLCSPBumpingProcessandCostConsiderations. . . . . . . . . 17 2.4 ReliabilityRequirementsforWLCSP. . . . . . . . . . . . . . . . . . . 20 2.5 StressinDropTest. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.6 StressinTMCL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.7 HighReliabilityWLCSPDesign. . . . . . . . . . . . . . . . . . . . . . . 22 2.8 TestChipDesignforPreciseReliabilityAssessment. . . . . . . . 23 2.9 BOPDesignRules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.10 RDLDesignRules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.11 ChapterSummary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ix