ElsevierUS Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page:1 InPraiseofVLSITestPrinciplesandArchitectures:DesignforTestability TestingtechniquesforVLSIcircuitsaretodayfacingmanyexcitingandcomplexchallenges. In the era of large systems embedded in a single system-on-chip (SOC) and fabricated in continuouslyshrinkingtechnologies,itisimportanttoensurecorrectbehaviorofthewhole system. Electronic design and test engineers of today have to deal with these complex and heterogeneoussystems(digital,mixed-signal,memory),butfewhavethepossibilitytostudy thewholefieldinadetailedanddeepway.Thisbookprovidesanextremelybroadknowledge ofthediscipline,coveringthefundamentalsindetail,aswellasthemostrecentandadvanced concepts. Itisatextbookforteachingthebasicsoffaultsimulation,ATPG,memorytesting,DFTand BIST.However,itisalsoacompletetestabilityguideforanengineerwhowantstolearnthe latest advances in DFT for soft error protection, logic built-in self-test (BIST) for at-speed testing,DRAMBIST,testcompression,MEMStesting,FPGAtesting,RFtesting,etc. MichelRenovell,Laboratoired’Informatique,deRobotiqueetdeMicroe´lectroniquede Montpellier(LIRMM),Montpellier,France This book combines in a unique way insight into industry practices commonly found in commercialDFTtoolsbutnotdiscussedintextbooks,andasoundtreatmentofthetechnical fundamentals. The comprehensive review of future test technology trends, including self- repair,softerrorprotection,MEMStesting,andRFtesting,leadsstudentsandresearchers toadvancedDFTresearch. Hans-JoachimWunderlich,UniversityofStuttgart,Germany Recent advances in semiconductor manufacturing have made design for testability (DFT) anessentialpartofnanometerdesigns.Thelackofanup-to-dateDFTtextbookthatcovers themostrecentDFTtechniques,suchasat-speedscantesting,logicbuilt-inself-test(BIST), testcompression,memorybuilt-inself-repair(BISR),andfuturetesttechnologytrends,has createdproblemsforstudents,instructors,researchers,andpractitionerswhoneedtomaster modern DFT technologies. I am pleased to find a DFT textbook of this comprehensiveness thatcanservebothacademicandprofessionalneeds. AndreIvanov,UniversityofBritishColumbia,Canada Thisisthemostrecentbookcoveringallaspectsofdigitalsystemstesting.Itisa“mustread” foranyonefocusedonlearningmoderntestissues,testresearch,andtestpractices. KewalK.Saluja,UniversityofWisconsin-Madison Design for testability (DFT) can no longer be considered as a graduate-level course. With growing design starts worldwide, DFT must be also part of the undergraduate curricu- lum.Thebook’sfocusonVLSItestprinciplesandDFTarchitectures,whiledeemphasizing test algorithms, is an ideal choice for undergraduate education. In addition, system-on- chip (SOC) testing is one among the most important technologies for the development of ultra-large-scale integration (ULSI) devices in the 21st century. By covering the basic DFT theoryandmethodologyondigital,memory,aswellasanalogandmixed-signal(AMS)test- ing, this book further stands out as one best reference book that equips practitioners with testableSOCdesignskills. YiheSun,TsinghuaUniversity,Beijing,China ElsevierUS Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page:xxii This Page is Intentionally Left Blank ElsevierUS Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page:3 VLSI T P EST RINCIPLES AND A RCHITECTURES ElsevierUS Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page:4 TheMorganKaufmannSeriesinSystemsonSilicon SeriesEditor:WayneWolf,PrincetonUniversity Therapidgrowthofsilicontechnologyandthedemandsofapplicationsareincreasinglyforcing electronicsdesignerstotakeasystems-orientedapproachtodesign.Thishasledtonewchallenges in design methodology, design automation, manufacture and test. The main challenges are to enhancedesignerproductivityandtoachievecorrectnessonthefirstpass.TheMorganKaufmann SeriesinSystemsonSiliconpresentshigh-quality,peer-reviewedbooksauthoredbyleadingexperts inthefieldwhoareuniquelyqualifiedtoaddresstheseissues. TheDesigner’sGuidetoVHDL,SecondEdition PeterJ.Ashenden TheSystemDesigner’sGuidetoVHDL-AMS PeterJ.Ashenden,GregoryD.Peterson,andDarrellA.Teegarden ReadingsinHardware/SoftwareCo-Design EditedbyGiovanniDeMicheli,RolfErnst,andWayneWolf ModelingEmbeddedSystemsandSoCs AxelJantsch ASICandFPGAVerification:AGuidetoComponentModeling RichardMunden MultiprocessorSystems-on-Chips EditedbyAhmedAmineJerrayaandWayneWolf ComprehensiveFunctionalVerification BruceWile,JohnGoss,andWolfgangRoesner CustomizableEmbeddedProcessors:DesignTechnologiesandApplications EditedbyPaoloIenneandRainerLeupers NetworksonChips:TechnologyandTools GiovanniDeMicheliandLucaBenini DesigningSOCswithConfiguredCores:UnleashingtheTensilicaDiamondCores SteveLeibson VLSITestPrinciplesandArchitectures:DesignforTestability EditedbyLaung-TerngWang,Cheng-WenWu,andXiaoqingWen ContactInformation CharlesB.Glaser SeniorAcquisitionsEditor Elsevier (MorganKaufmann;AcademicPress;Newnes) (781)313-4732 [email protected] http://www.books.elsevier.com WayneWolf Professor ElectricalEngineering,PrincetonUniversity (609)258-1424 [email protected] http://www.ee.princeton.edu/∼wolf/ ElsevierUS Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page:5 VLSI T P EST RINCIPLES A AND RCHITECTURES D T ESIGN FOR ESTABILITY Edited by Laung-Terng Wang Cheng-Wen Wu Xiaoqing Wen AMSTERDAM•BOSTON•HEIDELBERG•LONDON NEWYORK•OXFORD•PARIS•SANDIEGO SANFRANCISCO•SINGAPORE•SYDNEY•TOKYO MorganKaufmannPublishersisanimprintofElsevier ElsevierUS Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page:6 AcquisitionsEditor CharlesB.Glaser PublishingServicesManager GeorgeMorrison ProductionEditor DawnmarieSimpson AssistantEditor MicheleCronin ProductionAssistant MelindaRitchie CoverDesign PaulHodgson CoverIllustration ©DennisHarms/GettyImages Composition IntegraSoftwareServices TechnicalIllustration IntegraSoftwareServices Copyeditor SarahFortener Proofreader PhyllisCoyneetal.ProofreadingServices Indexer BroccoliInformationManagement Interiorprinter TheMaple-VailBookManufacturingGroup Coverprinter PhoenixColorCorporation MorganKaufmannPublishersisanimprintofElsevier. 500SansomeStreet,Suite400,SanFrancisco,CA94111 Thisbookisprintedonacid-freepaper. ©2006byElsevierInc.Allrightsreserved. Designationsusedbycompaniestodistinguishtheirproductsareoftenclaimedastrademarks orregisteredtrademarks.InallinstancesinwhichMorganKaufmannPublishersisawareofaclaim, theproductnamesappearininitialcapitalorallcapitalletters.Readers,however,shouldcontact theappropriatecompaniesformorecompleteinformationregardingtrademarksandregistration. Nopartofthispublicationmaybereproduced,storedinaretrievalsystem,ortransmittedinanyform orbyanymeans—electronic,mechanical,photocopying,scanning,orotherwise—withoutprior writtenpermissionofthepublisher. PermissionsmaybesoughtdirectlyfromElsevier’sScience&TechnologyRightsDepartmentinOxford, UK:phone:(+44)1865843830,fax:(+44)1865853333,E-mail:[email protected]. YoumayalsocompleteyourrequestonlineviatheElsevierhomepage(http://elsevier.com),byselecting “Support&Contact”then“CopyrightandPermission”andthen“ObtainingPermissions.” LibraryofCongressCataloging-in-PublicationData VLSItestprinciplesandarchitectures:designfortestability/editedby Laung-TerngWang,Cheng-WenWu,XiaoqingWen. p.cm. Includesbibliographicalreferencesandindex. ISBN-13:978-0-12-370597-6(hardcover:alk.paper) ISBN-10:0-12-370597-5(hardcover:alk.paper) 1. Integratedcircuits—Verylargescaleintegration—Testing. 2. Integratedcircuits—Verylarge scaleintegration—Design. I. Wang,Laung-Terng. II. Wu,Cheng-Wen,EEPh.D. III. Wen,Xiaoqing. TK7874.75.V5872006 621.39(cid:3)5—dc22 2006006869 ISBN13:978-0-12-370597-6 ISBN10:0-12-370597-5 ForinformationonallMorganKaufmannpublications, visitourWebsiteatwww.mkp.comorwww.books.elsevier.com PrintedintheUnitedStatesofAmerica 06 07 08 09 10 5 4 3 2 1 Working together to grow libraries in developing countries www.elsevier.com | www.bookaid.org | www.sabre.org ElsevierUS Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page:vii C ONTENTS Preface xxi In the Classroom xxiv Acknowledgments xxv Contributors xxvii About the Editors xxix 1 Introduction 1 YinghuaMinandCharlesStroud 1.1 Importance of Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Testing During the VLSI Lifecycle . . . . . . . . . . . . . . . . . . . . 2 1.2.1 VLSI Development Process. . . . . . . . . . . . . . . . . . . . 3 1.2.1.1 Design Verification . . . . . . . . . . . . . . . . . . 4 1.2.1.2 Yield and Reject Rate . . . . . . . . . . . . . . . . . 5 1.2.2 Electronic System Manufacturing Process . . . . . . . . . . . 6 1.2.3 System-Level Operation . . . . . . . . . . . . . . . . . . . . . 6 1.3 Challenges in VLSI Testing . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.1 Test Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.2 Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.2.1 Stuck-At Faults . . . . . . . . . . . . . . . . . . . . 12 1.3.2.2 Transistor Faults . . . . . . . . . . . . . . . . . . . 15 1.3.2.3 Open and Short Faults . . . . . . . . . . . . . . . . 16 1.3.2.4 Delay Faults and Crosstalk . . . . . . . . . . . . . . 19 1.3.2.5 Pattern Sensitivity and Coupling Faults . . . . . . 20 1.3.2.6 Analog Fault Models . . . . . . . . . . . . . . . . . 21 1.4 Levels of Abstraction in VLSI Testing . . . . . . . . . . . . . . . . . . 22 1.4.1 Register-Transfer Level and Behavioral Level . . . . . . . . . 22 1.4.2 Gate Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.3 Switch Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.4 Physical Level . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ElsevierUS Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page:viii viii Contents 1.5 Historical Review of VLSI Test Technology . . . . . . . . . . . . . . . 25 1.5.1 Automatic Test Equipment. . . . . . . . . . . . . . . . . . . . 25 1.5.2 Automatic Test Pattern Generation . . . . . . . . . . . . . . . 27 1.5.3 Fault Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.4 Digital Circuit Testing . . . . . . . . . . . . . . . . . . . . . . 28 1.5.5 Analog and Mixed-Signal Circuit Testing . . . . . . . . . . . 29 1.5.6 Design for Testability . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.7 Board Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5.8 Boundary Scan Testing . . . . . . . . . . . . . . . . . . . . . . 32 1.6 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2 Design for Testability 37 Laung-Terng(L.-T.)Wang,XiaoqingWen,andKhaderS.Abdel-Hafez 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2 Testability Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2.1 SCOAP Testability Analysis . . . . . . . . . . . . . . . . . . . 41 2.2.1.1 Combinational Controllability and Observability Calculation . . . . . . . . . . . . . . . 41 2.2.1.2 Sequential Controllability and Observability Calculation . . . . . . . . . . . . . . . 43 2.2.2 Probability-Based Testability Analysis . . . . . . . . . . . . . 45 2.2.3 Simulation-Based Testability Analysis . . . . . . . . . . . . . 47 2.2.4 RTL Testability Analysis . . . . . . . . . . . . . . . . . . . . . 48 2.3 Design for Testability Basics . . . . . . . . . . . . . . . . . . . . . . . . 50 2.3.1 Ad Hoc Approach . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.3.1.1 Test Point Insertion . . . . . . . . . . . . . . . . . . 51 2.3.2 Structured Approach . . . . . . . . . . . . . . . . . . . . . . . 53 2.4 Scan Cell Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.1 Muxed-D Scan Cell . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.2 Clocked-Scan Cell . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.4.3 LSSD Scan Cell . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.5 Scan Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.5.1 Full-Scan Design. . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.5.1.1 Muxed-D Full-Scan Design . . . . . . . . . . . . . . 59 2.5.1.2 Clocked Full-Scan Design . . . . . . . . . . . . . . 62 2.5.1.3 LSSD Full-Scan Design . . . . . . . . . . . . . . . . 62 2.5.2 Partial-Scan Design . . . . . . . . . . . . . . . . . . . . . . . . 64 2.5.3 Random-Access Scan Design . . . . . . . . . . . . . . . . . . 67 2.6 Scan Design Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.6.1 Tristate Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.6.2 Bidirectional I/O Ports . . . . . . . . . . . . . . . . . . . . . . 71 ElsevierUS Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page:ix Contents ix 2.6.3 Gated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.6.4 Derived Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.6.5 Combinational Feedback Loops . . . . . . . . . . . . . . . . . 74 2.6.6 Asynchronous Set/Reset Signals . . . . . . . . . . . . . . . . . 75 2.7 Scan Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.7.1 Scan Design Rule Checking and Repair . . . . . . . . . . . . 77 2.7.2 Scan Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.7.2.1 Scan Configuration . . . . . . . . . . . . . . . . . . 79 2.7.2.2 Scan Replacement . . . . . . . . . . . . . . . . . . . 82 2.7.2.3 Scan Reordering . . . . . . . . . . . . . . . . . . . . 82 2.7.2.4 Scan Stitching . . . . . . . . . . . . . . . . . . . . . 83 2.7.3 Scan Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.7.4 Scan Verification . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.7.4.1 Verifying the Scan Shift Operation . . . . . . . . . 85 2.7.4.2 Verifying the Scan Capture Operation . . . . . . . 86 2.7.5 Scan Design Costs . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.8 Special-Purpose Scan Designs . . . . . . . . . . . . . . . . . . . . . . . 87 2.8.1 Enhanced Scan . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.8.2 Snapshot Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.8.3 Error-Resilient Scan . . . . . . . . . . . . . . . . . . . . . . . 90 2.9 RTL Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . 92 2.9.1 RTL Scan Design Rule Checking and Repair . . . . . . . . . 93 2.9.2 RTL Scan Synthesis . . . . . . . . . . . . . . . . . . . . . . . . 94 2.9.3 RTL Scan Extraction and Scan Verification . . . . . . . . . . 95 2.10 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.11 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3 Logic and Fault Simulation 105 Jiun-LangHuang,JamesC.-M.Li,andDuncanM.(Hank)Walker 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.1.1 Logic Simulation for Design Verification . . . . . . . . . . . 106 3.1.2 Fault Simulation for Test and Diagnosis . . . . . . . . . . . . 107 3.2 Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.2.1 Gate-Level Network . . . . . . . . . . . . . . . . . . . . . . . . 109 3.2.1.1 Sequential Circuits . . . . . . . . . . . . . . . . . . 109 3.2.2 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.2.2.1 Unknown State u . . . . . . . . . . . . . . . . . . . 111 3.2.2.2 High-Impedance State Z . . . . . . . . . . . . . . . 113 3.2.2.3 Intermediate Logic States . . . . . . . . . . . . . . 114 3.2.3 Logic Element Evaluation . . . . . . . . . . . . . . . . . . . . 114 3.2.3.1 Truth Tables . . . . . . . . . . . . . . . . . . . . . . 115 3.2.3.2 Input Scanning . . . . . . . . . . . . . . . . . . . . 115