PreprinttypesetinJINSTstyle-HYPERVERSION The Planck/LFI Radiometer Electronics Box Assembly 0 1 0 2 J. M.Herrerosa, M.F.Gómeza,R.Reboloa,b∗,H.Chulania,J. A.Rubiño-Martina, n S. R.Hildebrandta, M.Bersanellic R.C. Butlerd, M.Miccolise, A.Peñaf,M. Pereiraf, a F.Torrerof,C. Franceschetc,M. Lópezf andC.Alcaláf J 6 aInstitutodeAstrofísicadeCanarias(IAC), 2 38200LaLaguna.Tenerife. Spain bConsejoSuperiordeInvestigacionesCientíficas,Spain ] M cUniversitádiMilano,DipartamentodiFisica, I ViaG.Celoria16,I-20133Milano,Italy . h d INAF-IASFBologna, p ViaP.Gobetti,101,I-40129Bologna,Italy - o eThalesAleniaSpaceItaliaS.p.A., r IUEL-ScientificInstruments,S.S.PadanaSuperiore290,20090Vimodrone(Mi)Italy t s f EADSAstriumCRISA,Madrid,Spain a [ E-mail: [email protected] 1 v 6 ABSTRACT: The Radiometer Electronics Box Assembly (REBA)is the control and data process- 9 ing on board computer of the Low Frequency Instrument (LFI)of the Planck mission (ESA).The 6 REBAwas designed and built incorporating state of the art processors, communication interfaces 4 . andrealtimeoperating systemsoftwareinordertomeetthescientificperformance oftheLFI.We 1 0 present atechnical summaryoftheREBA,including aphysical, functional, electrical, mechanical 0 andthermaldescription. Aspectsofthedesignanddevelopment, theassembly, theintegration and 1 : theverification oftheequipment areprovided. Abriefdescription oftheLFIonboard software is v i given including the Low-Level Software and the main functionalities and architecture of the Ap- X plicationSoftware. Thecompressormodule,whichhasbeendevelopedasanindependentproduct, r a laterintegratedintheapplication, isalsodescribedinthispaper. Twoidenticalengineering models EMandAVM,theengineeringqualificationmodelEQM,theflightmodelFMandflightsparehave beenmanufacturedandtested. Low-levelandApplicationsoftwarehavebeendeveloped. Verifica- tion activities demonstrated that the REBAhardware and software fulfil all the specifications and perform asrequired forflightoperation. KEYWORDS: CosmicMicrowaveBackground –spacemission–DataHandling- DigitalSignal Processing -DataCompression –DataAcquisition -Low-Level Software–SpaceWire- MIL-STD-1553B. ∗ Correspondingauthor. Contents 1. Introduction 2 2. Equipmentoverview 2 2.1 DSPmodule 4 2.2 Auxiliaryboard 6 2.3 DAUfunction 8 2.4 DC/DCConverter 9 2.5 Grounding concept 10 2.6 Redundancy 10 3. Mechanicalandthermaldesigndescription 11 4. Design,developmentandAIV 13 5. REBAOn-boardsoftware overview 16 5.1 REBALow-levelSoftware 17 5.2 REBAApplication Software 18 5.2.1 Functionalities 18 5.2.2 Architecture 20 5.2.3 VerificationandValidation 20 5.2.4 Metrics 20 6. TheSPUCompressorModule 21 6.1 Compressorrequirements 21 6.2 Compressorgeneral architecture 21 6.3 Performancevalidation andresults 22 7. Conclusions 23 A. Abbreviationsandacronyms 25 B. DPU_ASWandSPW_ASWarchitectures 26 –1– 1. Introduction The Low Frequency Instrument (LFI, Bersanelli et al. 2009; Mandolesi et al. 2009) of the ESA satellitePlanckconsistsofanarrayof11corrugatedhornsfeeding22polarisationsensitivepseudo- correlation radiometers based on HEMT transistors and MMIC technology. These are actively cooleddownto20Kbyusinganewconceptsorptioncooler. Theradiometerscoverthreefrequency bands centred at 30 GHz, 44 GHz, and 70 GHz. The LFI shares the focal plane of the 1.5m- aperturePlancktelescopewiththeHighFrequencyInstrument(HFI),whichisbasedonbolometric detectors cooled to 0.1 K (Lamarre et al. 2009). The combination of LFI and HFI is designed to provide full-sky maps of the microwave sky with an unprecedented combination of spectral coverage (30-850 GHz), sensitivity (D T/T ∼ 2×10−6), angular resolution (∼ 10 arcmin) and suppression ofsystematiceffects. Each LFI radiometer correlates the signal from the sky with that of a reference blackbody source cooled to 4 K. At the end of the radiometric chain, the amplified signals are detected by square law diodes, DC amplified and transmitted to the Data Acquisition Electronics (DAE) for signalconditioning anddigitization. TheLFIarrayrequired adedicated electronic system toperform on-board instrument control, commandanddatahandling aswellastheon-board scientificdataprocessing withhighreliability androbustness. Thesefunctions arecarried outbytheLFIRadiometer Electronics BoxAssembly (REBA),which isdescribed indetail inthis paper. Inparticular, the REBAincorporates the com- pression algorithms needed tooptimize the useofthesatellite toground available communication bandwidth. Theexpected output ofLFIis5.7Mbpswhilethe available effective bandwidth isthe order of 53 kbps, implying aneed for on board pre-processing of the raw data. Themost relevant physical, functional, electrical, mechanicalandthermalcharacteristics oftheREBA,aswellasthe mainsoftwareaspects, aredescribed indetailinthefollowing sections. Forabroad description of the REBA in the context of LFI, see Section 4.4.2 in Bersanelli et al. (2009) on the DAE and its connection withREBA. 2. Equipment overview The REBA is a warm electronics unit consisting of two separate identical units, one nominal and one redundant, which operate in cold redundancy under power supply control of the spacecraft. Each unit has an envelope of 270×233×108 mm3, is painted in matblack with an emissivity of 0.9,andweights4.32Kg(seeFigure1). ThemeasuredpowerconsumptionoftheREBAis22.7W fully running and processing science data, while the measured total power consumption of LFI is 68.3 W. Each unit houses three stacked electronics modules and they are located on the lateral panelsoftheservicemodule(SVM)ofthespacecraft atabout300K. Each REBA unit is connected to the instrument Data Adquisition Electronics (DAE) in the Radiometer Array Assembly (RAA) through the instrument harness and to the spacecraft Central DataManagementUnit(CDMU)andPowerControlDistribution Unit(PCDU)throughthespace- craft harness. Figure 2 shows the connections between the REBAnominal unit, the DAE and the spacecraft CDMUandPCDU. –2– Figure1. REBAnominalandredundantflightmodels. The REBA incorporates very innovative advances in several areas, remarkably: i) new DSP processors like TSC21020E which were considered among the most advanced high-performance processors(18MHzand0waitstate-EDACprotected)forscientificapplicationinspacemissions; ii) very high velocity serial communications interfaces and, iii) new real time on-board operating system. TheREBAprovidesthehardwaretoperformthefollowingmainfunctions: • On-board commandanddatahandling. • On-board sciencedataprocessing andcompression. • Instrument control. • Communication withthespacecraft CDMUviaaMIL-STD-1553BCDMSbusinterface. • CommunicationwiththeLFIsubsystemDAEviafourIEEE-1355full-duplex,bi-directional, serial, point-to-point datalinks. • Hardwareinitialisation anderrormanagement. • MemoryErrorDetectionandCorrection (EDAC). • Computer watchdog activity control. Internal on-board time management and synchronisa- tionwiththeCDMS. • DAEsynchronisation. • On-board softwarestorage andprocessing. • Internal housekeeping dataacquisition. • S/CPowerconditioning andinternalpowerdistribution. • DigitalInput/Output interface withtheDAEforcontrolpurposes. These functions are allocated to four functional units: the Data Processing Unit (DPU), the SignalprocessingUnit(SPU),theDataAcquisitionUnit(DAU),andthePowersupplyUnit(PSU). TheDPUandSPUareinchargeofthetelecommand,housekeepingandsciencetelemetryprocess- ing and provide the functions to ensure that the hardware and software operate as planned. The –3– Figure2. LFIfunctionalblockdiagram(nominal). DAUperformstheanaloguetodigitalconversionofthehousekeepingoftheREBAitself,whilethe switching regulator of the PSU provides galvanic isolation converting the spacecraft (S/C) power bus voltage to a series of current limited, under/over voltage protected regulated voltages for the sectionsoftheREBA.ItperformsthecontroloftheDC/DCconverterswitchinganddistributesthe electricalpowertotheSPUsub-units(DPU,SPUandDAU).Figure3showsasimplifiedfunctional blockdiagram oftheREBA. TheREBAiscomposedofthreeboards,twoDSPboardsandoneboardfortheDAEinterface function and the DC/DC Converter. The DPU Digital Signal Processor (DSP) board is in charge of the control of the different elements: its software controls the DAU board by means of the Internal Bus and it also controls the SPU DSP board by an external spacewire connection. The DC/DC converter supplies all the functions. Table 1 shows the DPU and SPU characteristics and performance. 2.1 DSPmodule TheProcessorModule-seeblockdiagraminFigure4-isaFloatingPointDigitalSignalProcessing CPUonasingleboardbasedontheDSPTSC21020F,radiationtolerantversionoftheADSP21020 from Analogue Devices. Its external and open Harvard architecture provides two complete bus systems for program (48 bits) and data (32 bits), allowing concurrent access and simultaneous fetchinganddataaccessesormultipledataaccessesonasingleclockcycle. Expansioncapabilities areprovidedviathebackpanelsystembusaswellasamezzanineauxiliaryinterface. TheProcessor Module implements into a single board: 6x32 Kbytes PROM, 256K x 64 bits EEPROM (EDAC protected), 512Kx56bitsprogramRAM(EDACprotected)and512Kx40bitsdataRAM(EDAC protected), 512K x 40 bits of Expansion RAM; three high-speed IEEE-1355 (SpaceWire) links, –4– Figure3. REBAfunctionalblockdiagram. asynchronous serialinterface;Expandedinterruptcapabilities; SystemBuscontrol;Programmable Watch-dog &system TimerandIEEE1149.1(JTAG)interface. GeneralFeatures: TSC21020FIEEE32/40bitsFloatingPointDigitalSignalProcessoratupto 18MHz,0waitstatesforRAM.Harvardarchitecture withindependent programanddatamemory buses. IEEE1149.1I/F(JTAG)fortestinganddebugging. On-chipemulation. 6x32Kx48bitsstart- –5– Table1. DPUandSPUcharacteristicsandperformances. Feature DPU SPU ProgramROMSize 32KWx48 32KWx48 ProgramRAMSize 512KWx48(0waitstate-EDACprotected) 512KWx48(0waitstate-EDACprotected) DataRAMSize 512KWx32(0waitstate-EDACprotected) 512KWx32(0waitstate-EDACprotected) Exp.DataRAMSize Notimplemented 512KWx32(0waitstate-EDACprotected) EEPROMSize 256KWx48 Notimplemented InterfacetoMILBUS IncludedinAuxiliaryBoard Notimplemented OBTtimer PMPSC PMPSC(Notused) Watchdogtimer DMPSC DMPSC SMCSInterface OneIFwiththreeLVDSchannels DSPOperation 18MHz InterfacetoDAU -EndofAcquisitionInterrupt Notimplemented -Internalanalogacquisitions -1HzInterrupt -ConverterSyncstatusinput -1Hzsignalcontrol InterfacetoDAE -DAEPowerStatusinput -DAEDatareadyInterrupt -DAEresetSMCS1output -DAEresetSMCS2output InterfacetoSPU -ResettoSPU -ResetfromDPU upPROM,256Kx64bitsEEPROMprogrambank(EDACprotected), 512Kx56bitsProgramRAM (EDACprotected) and 512Kx40 bitsDataRAMplusanoptional 512Kx40 Expansion RAMbank (both banks EDAC protected). 6 Interrupt levels (4 of them through the System Bus) and IEEE Exception HandlingwithInterrupt onException. Bi-directional IEEE-1355(SpaceWire)basedon SMCS332 and LVDS drivers capable of 100 Mbps data rates. Programmable Watch-Dog and 32 bitsystemTimers. PowerandResetmonitor. SystemBusInterface(Master). UnitMonitoringand Controlcapabilities throughSystemBus. Standarddevelopment toolsfromAnalogDevices. KeyDesignFeatures: Performance (at18MHz): 18MIPS,54MFLOPS(peak) 36MFLOPS (sustained). EDAC,UART,Timers,GeneralpurposeI/OregistersandGluelogicintegratedintothe ProcessorSupportChip(PSC)ASICdesignedanddevelopedbyCRISA.Highdegreeofexpansion, compatibility and configurability through the system bus interface and Auxiliary bus interfaces: The System Bus interface has been designed for connecting the DSP to maximise the expansion possibilities (I/O modules, etc.). The Auxiliary bus interface has been designed for connection of amezzanine auxiliary boardoriginally intended forhighspeedinterfaces suchasthe1553/OBDH businterface, EEPROM/RAMexpansion, etc. The purpose of the PSC Chip is: To enhance the on-chip memory management capabilities of the DSP, providing additional address decoding and wait state generator. Four IO Areas are providedperdecodingbank. ToprovideaflowthroughEDAC,configurableinwidthandenabling per I/O Area. To provide a simple 32 bit programmable Timer. To provide a Complex Timer configurable to provide a System Watchdog or an On-Board Time (OBT) support counter-timer. To provide a high speed UART. To provide buffer control in order to support the implementation of extension buses. The design of the PSC is compatible with the use in the PMB and DMB. It considers thebitaligning andbuswideness. 2.2 Auxiliaryboard The 1553B Interface function is responsible for the communication between the DPU and the –6– Figure4. DSPboarddiagram. CDMS.Aspart of theDPUboard, this block is implemented on anindependent board inserted in the Auxiliary Connector of the DPU board itself. The block diagram of this function is shown in Figure 5. The external connection is of course to the 1553B Data bus. As required by the MIL- STD-1553standard,theconnectionismadetobothbuses,andtheimplementationisbytransformer coupling. TheRemoteTerminalAddress, isdiscrepant tothestandard being internally hardwired, andisdifferentfortheNominalandRedudantUnits. Thearchitecture ofthe1553Binterface isbuiltaroundtheDDCBU61582. Thishardenedde- viceprovidesacompletelyintegratedBC/RT/MTinterfacebetweenthehostprocessorandthebus, although its use in the REBAis reduced to Remote Terminal mode. It integrates dual transceiver, protocol, memory management and processor interface logic. It also includes internal 16Kwords ofRAMwhichisnotusedinthedesignduetoitsverylowspeedcharacteristics. TheinterfacefordatawiththeDPUsoftwareisperformedbymeansofaDual-PortRAM.The software canalsoaccess theinternal BU61582internal registers, andanacknowledge generator is included to allow access even in case the component is processing commands. This circuit also ensures noconflictappearsintheaccessestotheDual-PortRAM. Theinterface alsoincludes circuitrytogenerateageneralDPUresetonreception ofaSA28R commandoverthebus. Theblockimplementssomelogictoavoidfeedbackproblemsbetweenthis resetline,thatissentdirectlytotheDPU,andthegeneralresetlinefromtheDPUthatisactivated immediately after. It introduces a delay allowing the transmission of the status response through the1553busafterthereception ofthecommand. The interface with the DPU board through the Auxiliary connector also includes a buffering stage which is not part of the DSP board. This stage decouples the internal Aux board operation –7– Figure5. AUXBoardBlockDiagram. fromtheDSPactivities. Thisboardusestwosecondaryvoltagessupplies: 5Vforthegenerallogic as well as for the BU61582 and −15V, a devoted DC/DCconverter output with its corresponding returnline. ThegenerallogicandDC/DCconverterreturnlinesareconnectedinordertodecouple thelargepeakcurrents relatedtothebuscommunications fromthegeneralsupplylines. 2.3 DAUfunction TheDAUisincluded onthePowerSupplyUnit(PSU)board together withtheDC/DCConverter. TheDAUacquirestheanaloguehousekeeping oftheREBAperforminganaloguesignalcondition- ing,digitalconversion, andtransmission totheDPUviathebackpanelconnector. Figure 6 shows the DAU functional blocks. The specific DAU functions are: Internal Bus Interface. Analogue to Digital Conversion. Acquisition Control. Clock Divider. Thermistors Conditioning. Secondary Currents Conditioning. Secondary Voltages Conditioning. Internal Test Voltages Conditioning. Status. TheDAUisaslavefunctioncontrolledbytheDPUmodule. TheDPUgeneratestheBuslines that handle the DAU by means of write and read bus cycles. The "Start of an acquisition cycle" signal is generated with a write command by the DPU. This command enables the Acquisition Control Block and starts acycle of acquisition. TheStatus Block contains the following informa- tion: “Acquisitioninprogress”bit,whenset,thisindicatesthatanacquisitioncyclewasstartedand hasnotstillfinished;whencleared,thisindicatesthatanacquisitioncyclefinishedandanewcycle can be started. FIFOFlags: Three bits that indicate the FIFO status (empty, not empty, full, etc.). OBTclockstatuswhichindictes iftheREBAOBTcounterisusingtheexternalorinternal clock. In the Analogue to Digital conversion block the analogue signals are routed to a 16 channel multiplexer stage of type HI-546. The selected signal is buffered by an OP-42 Operational Am- plifier and applied to the input of an Analogue to Digital Converter (ADC) type AD-574. The 9 mostsignificantbitsoutputoftheADCarestoredinaFIFOmemory. Themethodofacquisitionis cyclic. OnceallthechannelshavebeensampledandplacedintheFIFOtheAcquisitioninProgress signalisdeactivated sothattheDPUcanreadoutthedata. –8– Figure6. DAUblockdiagram. The RS-422 block of the DAU provides the interface to the DAE for the 1 Hz time synchro- nisation signal used by the DAE at power up and during the process of time synchronisation with the OBT.Thesignal isderived from the2Hzsignal generated bythe CPU.Itsphase iscontrolled (by DPU software and by means of two signals) in order to ensure a rising edge when required, bothatpowerupandduringthesynchronization procedure. Threetemperaturemonitoringteleme- tries are provided by the DAU function: the DPU board temperature, the SPU board temperature and the PSU board temperature, using NTC type thermistor. Four secondary voltage monitoring telemetries areprovided bytheDAUfunction: theVCCvoltage (logic supply), the+15Vvoltage (positiveanalogue supply)andthe−15Vvoltage(negativeanalogue supply), andthe−15V_1553 voltage. The currents of these secondary voltages, sensed at the active path of the secondary, are alsoprovided. Eachconditioning circuitry includes afilterwith fc=100Hz. 2.4 DC/DCConverter Figure7isablockdiagram oftheDC/DCConverter whichusesthebuckfedtopology commonly used in space programs. Theconverter operation starts once the power bus ispresent atthe input. There is no command to turn On or Off the converter. The “Buck stage” provides the voltage regulationattheoutputwhilethe“push-pullstage”transformsthevoltagetotheoutputlevels. The converter has both common mode and differential mode filters to reduce the emissions onto the mainbusasshownintheblockdiagram. Once the PDUt power bus is available, the converter turns On in a smooth manner because the inrush current is limited by means of an external latching current limiter in the PDU to avoid –9–