THE BOUNDARY-SCAN HANDBOOK SECOND EDITION Analog and Digital THE BOUNDARY-SCAN HANDBOOK SECOND EDITION Analog and Digital by Kenneth P. Parker Hewlett-Packard Company KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW eBookISBN: 0-306-47656-8 Print ISBN: 0-7923-8277-3 ©2002 Kluwer Academic Publishers NewYork, Boston, Dordrecht, London, Moscow Print ©1998 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook maybe reproducedor transmitted inanyform or byanymeans,electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: http://kluweronline.com and Kluwer's eBookstore at: http://ebooks.kluweronline.com Dedication This book is dedicated to the memory of an Uncle for whom I was namesake. Kenneth Fredric Parker, 1912-1998 TABLE OF CONTENTS List of Figures xiii List of Tables xviii List of Design-for-Test Rules xix Preface to the First Edition xxi Preface to the Second Edition xxiii Acknowledgement xxv 1 Boundary-Scan Basics and Vocabulary 1 1.1 Digital Test Before Boundary-Scan 2 1.1.1 Edge-Connector Functional Testing 2 1.1.2 In-Circuit Testing 4 1.2 The Philosophy of 1149.1-1990 7 1.3 Basic Architecture 8 1.3.1 The TAP Controller 10 1.3.2 The Instruction Register 16 1.3.3 Data Registers 20 1.3.4 The Boundary Register 21 1.3.5 Optimizing a Boundary Register Cell Design 27 1.3.6 Architecture Summary 29 1.3.7 Field-Programmable IC Devices 30 1.3.8 Boundary-Scan Chains 31 1.4 Non-Invasive Operational Modes 32 1.4.1 BYPASS 33 1.4.2 IDCODE 33 1.4.3 USERCODE 34 1.4.4 SAMPLE 35 1.4.5 PRELOAD 35 1.5 Pin-Permission Operational Modes 36 1.5.1 EXTEST 36 1.5.2 INTEST 37 1.5.3 RUNBIST 38 1.5.4 HIGHZ 39 1.5.5 CLAMP 39 1.5.6 Exceptions Due to Clocking 39 1.6 Extensibility 40 1.7 Subordination of IEEE 1149.1 41 1.8 Costs and Benefits 42 1.8.1 Costs 42 1.8.2 Benefits 43 1.8.3 Trends 45 1.9 Other Testability Standards 46 2 Boundary-Scan Description Language (BSDL) 49 2.1 The Scope of BSDL 52 2.1.1 Testing 52 2.1.2 Compliance Assurance 53 2.1.3 Synthesis 55 2.2 Structure of BSDL 57 2.3 Entity Descriptions 61 2.3.1 Generic Parameter 62 2.3.2 Logical Port Description 62 2.3.3 Standard USE Statement 63 2.3.4 Use Statements 64 2.3.5 Component Conformance Statement 64 2.3.6 Device Package Pin Mappings 65 2.3.7 Grouped Port Identification 66 2.3.8 TAP Port Identification 67 2.3.9 Compliance Enable Description 68 2.3.10 Instruction Register Description 69 2.3.11 Optional Register Description 70 2.3.12 Register Access Description 71 2.3.13 Boundary-Scan Register Description 72 2.3.14 RUNBIST Execution Description 75 2.3.15 INTEST Execution Description 76 2.3.16 User Extensions to BSDL 77 2.3.17 Design Warnings 77 2.4 Some advanced BSDL Topics 78 2.4.1 Merged Cells 78 2.4.2 Asymmetrical Drivers 80 2.5 BSDL Description of 74BCT8374 80 2.6 Packages and Package Bodies 84 2.6.1 STD_1149_1_1999 85 2.6.2 Cell Description Constants 89 2.6.3 Basic Cell Definitions BC_0 to BC_7 91 2.6.4 User-Defined Boundary Cells 99 2.6.5 Definition of BSDL Extensions 100 2.7 Writing BSDL 101 2.8 Summary 103 3 Boundary-Scan Testing 105 3.1 Basic Boundary-Scan Testing 106 3.1.1 The 1149.1 Scanning Sequence 106 3.1.2 Basic Test Algorithm 112 3.1.3 The “Personal Tester” Versus ATE 113 3.1.4 In-Circuit Boundary-Scan 114 3.1.5 IC Test 116 3.1.6 IC BIST 118 viii 3.2 Testing with Boundary-Scan Chains 119 3.2.1 1149.1 Chain Integrity 119 3.2.2 Interconnect Test 122 3.2.3 Connection Tests 136 3.2.4 Interaction Tests 138 3.2.5 BIST and Custom Tests 141 3.3 Porting Boundary-Scan Tests 142 3.4 Summary 144 4 Advanced Boundary-Scan Topics 145 4.1 DC Parametric IC Tests 146 4.2 Sample Mode Tests 147 4.3 Concurrent Monitoring 150 4.4 Non-Scan IC Testing 151 4.5 Non-Digital Device Testing 154 4.6 Mixed Digital/Analog Testing 155 4.7 Multi-Chip Module Testing 157 4.8 Firmware Development Support 159 4.9 In-System Configuration 160 4.10 Hardware Fault Insertion 163 5 Design for Boundary-Scan Test 167 5.1 Integrated Circuit Level DFT 169 5.1.1 TAP Pin Placement 169 5.1.2 Power andGround Distribution 170 5.1.3 Instruction Capture Pattern 174 5.1.4 Damage Resistant Drivers 175 5.1.5 Output Pins 176 5.1.6 Bidirectional Pins 177 5.1.7 Post-Lobotomy Behavior 178 5.1.8 IDCODEs 178 5.1.9 User-Defined Instructions 179 5.1.10 Creation and Verification of BSDL 180 5.2 Board-Level DFT 182 5.2.1 Chain Configurations 182 5.2.2 TCK/TMS Distribution 185 5.2.3 Mixed Logic Families 186 5.2.4 Board Level Conflicts 187 5.2.5 Control of Critical Nodes 188 5.2.6 Power Distribution 190 5.2.7 Boundary-Scan Masters 190 5.2.8 Post-Lobotomy Board Behavior 192 5.3 System-Level DFT 193 5.3.1 The MultiDrop Problem 194 5.3.2 Coordination with Other Standards 195 5.4 Summary 195 ix 6 Analog Measurement Basics 197 6.1 AnalogIn-CircuitTesting 197 6.1.1 Analog Failures 198 6.1.2 Measuring an Impedance 200 6.1.3 Errors and Corrections 204 6.1.4 Measurement Hardware 206 6.2 Limited Access Testing 211 6.2.1 NodeVoltageAnalysis 212 6.2.2 Testing With Node Voltages 213 6.2.3 Limited Access Node Voltage Testing 215 6.3 The Mixed-Signal Test Environment 217 6.4 Summary 220 7 IEEE 1149.4 Analog Boundary-Scan 221 7.1 1149.4 Vocabulary and Basics 222 7.1.1 The Target Fault Spectrum 223 7.1.2 Extended Interconnect 223 7.1.3 Digital Pins 225 7.1.4 Analog Pins 226 7.2 General Architecture of an 1149.4 IC 227 7.2.1 Silicon “Switches” 229 7.2.2 The Analog Test Access Port (ATAP) 230 7.2.3 The Test Bus Interface Circuit (TBIC) 231 7.2.4 The Analog Boundary Module (ABM) 236 7.2.5 The Digital BoundaryModule (DBM) 242 7.3 The 1149.4 Instruction Set 243 7.3.1 The EXTEST Instruction 244 7.3.2 The CLAMP Instruction 247 7.3.3 The HIGHZ Instruction 247 7.3.4 The PROBE Instruction 247 7.3.5 The RUNBIST Instruction 248 7.3.6 The INTEST Instruction 248 7.4 Other Provisions of 1149.4 250 7.4.1 DifferentialATAP Port 250 7.4.2 Differential I/O 251 7.4.3 Partitioned Internal Test Buses 253 7.4.4 Specifications and Limits 256 7.5 Design for 1149.4 Testability 257 7.5.1 Integrated Circuit Level 257 7.5.2 Board Level 259 7.5.3 System Level 260 7.6 Summary 261 7.7 Epilog: What Next for 1149.1/1149.4? 262 x APPENDIXA: BSDLSyntaxSpecifications 263 A.1 Conventions 263 A.2 Lexical elements of BSDL 264 A.3 Notes on syntax definition 267 A.4 BSDL Syntax 269 A.5 User Package Syntax 273 Bibliography 275 Index 281 xi List of Figures Figure 1-1: In-Circuit test setup with full nodal access. The component under test may be embedded within a board and connected to other components. 5 Figure 1-2: Cutaway drawing of a board resting on top of an In-Circuit, vacuum- actuated test fixture: the “bed of nails.” The module interface pins are the mechanical interface to the ATE pin electronics, which are placed very close to reduce path lengths. 6 Figure 1-3: General, simplified architecture of an 1149.1 compliant Integrated Circuit. 9 Figure 1-4: State transition diagram of the sixteen-state TAP controller. 11 Figure 1-5: Architecture detail of a typical Boundary-Scan register with shift and parallel hold ranks. 17 Figure 1-6: Example of an instruction register cell design. The expanded cell shows several control signals generated by the TAP state machine. 19 Figure 1-7: A Typical Boundary Register Cell. 22 Figure 1-8: A Bidirectional pin with separate input and output Boundary Register cells. 23 Figure 1-9: A Bidirectional pin served by a reversible Boundary Register cell. 25 Figure 1-10: Compensating inversions in an input Boundary Register cell that monitors an inverting input buffer. 26 Figure 1-11: Compensating inversion in an output Boundary Register cell connected to an inverting output buffer. 26 Figure 1-12: Two logical symbols for typical boundary cells, one with an Update (UPD) flip-flop (A) and one without (B). 27 Figure 1-13: An example (adapted from [Whet95]) of an output cell design that eliminates both a discrete register stage and a multiplexer delay. 28 Figure 1-14: Block Diagram of a Boundary-Scan IC. 29 Figure 1-15: A field-programmable component with Boundary-Scan hard-wired into its I/O Blocks (IOBs). Each IOB starts out with bidirectional support for a component pin, but subsequent programming may reduce each to supporting input or output only. 31 Figure 1-16: A simple chain of Boundary-Scan ICs. 32 Figure 1-17: Code bit allocation in a Device Identification Register accessed by IDCODE. 34 Figure 1-18: Observe-Only Boundary Register cell for inputs. 40 Figure 1-19: Product introductions by Companies X and Y, and their relative performance. 44 Figure 2-1: BSDL use model within or outside of a VHDL environment. 51 Figure 2-2: BSDL used as a test driver. 53 Figure 2-3: A process for checking the compliance of an IC with the Standard. 54 Figure 2-4: An 1149.1 synthesis system that both creates and uses BSDL. 56 Figure 2-5: The relationship of a BSDL entity to the standard package and package body. 59 Figure 2-6: Candidate for merged cell design. 78 Figure 2-7: Design with input and control cells merged. 79 Figure 2-8: A design illustratingseveral merged cell situations. 81 Figure 2-9: Texas Instruments 74BCT8374 Octal D Flip-Flop with Boundary-Scan. 82