1 Precharge Logic Basics 1.1 Introduction The purpose of this book is to describe the issues involved in precharge circuit design and to establish design guidelines that will minimize the design risk. Anyonedesigningdynamiccircuitsorfullswingmemoriesshouldreadthisbook. There are many logic families utilizing the metal oxide semiconductor (MOS) transistor. Static complementary metal oxide semiconductor (CMOS) is the most widely used, partly because it is safe. “Safe” means that it will almost always work without any special considerations. However, sometimes static logic just is not good enough. In advanced very large scale integration (VLSI) systems such as microprocessors, there arise “critical” logic paths where static logic is just tooslow to meet the timing constraints. There are faster logic families, and precharge (dynamic) logic [1] is one of them. Precharge logic also has other advantages over staticlogic [37].Ofcourse,thereare alsodisadvantages,anddesignwithprecharge logicismorechallengingtoensurepropercircuitoperation. Thisbookcoverssynchronous(clocked)prechargelogic.“Clocked”simplymeans that the clock is used to (indirectly) precharge the outputs of the logic gates. There existsalsoasynchronousprechargelogic,buttheclockedversionissimplerandmore popular. This type of logic is widely called “dynamic” logic in the industry, where “dynamic” simply means relying on charge storage, and “static” means “always driven.”Butbecause“keepers”canbeaddedtothedynamicnodes,thistypeoflogic can be dynamic or static. Thus, “precharge logic” appears to be a more appropriate name.KeeperswillbeexplainedindetailinSection1.7andinChapter3. 1.2 What Is Precharge Logic? A basic precharged NAND gate is shown in Figure 1.1. The logic gate consists of an N-channel metal oxide semiconductor (NMOS) tree of transistors known as the “pulldown stack.” The output is precharged HIGH by the P-channel metal oxide semiconductor (PMOS)device whenthe clockis LOW. Theoutputis conditionally discharged when the clock turns on the NMOS device connected to ground. This is known as the evaluation device or “footer.” Discharge of the output happens when the clock is HIGH and the inputs create a path in the NMOS tree from the output node to the bottom NMOS device. The clock can be replaced with a signal named “/precharge,” as in the general case the precharge/evaluate functions can be SynchronousPrechargeLogic. ©2012ElsevierInc.Allrightsreserved. 2 SynchronousPrechargeLogic Figure1.1 Basicprechargedgate(NAND)with dynamicoutput. Clock (Precharge) Output (Dynamic node) Evaluate Precharge Evaluate Clock1 (Phase 1 logic) Clock2 (Phase 2 logic) Precharge Evaluate Precharge Figure1.2 Clockphasedefinition. controlled with any signal. An example would be an asynchronous system where there are no clocks. In any case, please note that we precharge HIGH and evaluate LOW because of the good efficiency of the NMOS devices. Predischarging LOW andevaluatingHIGHwouldnotbeasefficient. Somecommontermsusedareasfollows(Figure1.2): theprechargephaseiswhentheclockinputtoacircuitislow, theevaluationphaseiswhentheclockinputtoacircuitishigh. 1.3 Why Is it Faster than Static Logic? Precharge logic gets its speed from the fact that the pullup tree (single P-channel field effect transistor (PFET)) and the pulldown tree are never on at the same time. When a static gate switches, there is an overlap time when the two trees are “fight- ing.” Precharge logic separates the pullup and pulldown times, as can be seen in Figure 1.3. If we want to discharge the output (pull it down), then the only current flowing in the NMOS tree is from the charge stored on the output node. In static logic, there is also a short circuit (crowbar) current that flows from V to V , and dd ss so the peak transition current in static logic is higher than in precharge logic. Because the crowbar current exists directly between V andV , itcan beseen that dd ss this current does no logical work and is therefore wasted power. More importantly, PrechargeLogicBasics 3 (A) (B) Static logic Precharge logic Fighting nt nt e e urr urr C C Time Time T Evaluation delay T phl phl Pfet current Nfet current Figure1.3 (A)StatictransitionHIGHtoLOW;(B)prechargelogicprechargeand discharge. as the current inthe metal oxide semiconductor field effect transistor(MOSFET) is not solely from the charge stored in the load capacitance, it takes longer to dis- chargetheloadinstaticlogic. Anotherfactorintheprechargelogicspeedupisthefactthatthedynamicnodestarts topulldownwhentheinputreachesthetransistorthresholdvoltageV.Thisissooner t thaninthestaticgate,whichbeginsswitchingwhentheinputreachesroughlyV /2. dd So the pulldown speed is improved considerably, even though there is typically an extra NMOS device in series with the NMOS logic tree. This is of course the clock-controlled footer, connected to V . The pullup time experiences the biggest ss improvement in speed because there is only one pullup device (as opposed to a series P stack). But because this is the precharge time, it is typically not critical andsotimingcanbeadjusteddependingonhowonesizesthedevice. Onemayaskhowthislogic canbefasterifawholehalfofaclockcycleisded- icated to precharging the output. The answer is that the whole picture must be con- sidered, meaning the logic and latches/registers separating the logic stages. In a typical two-phase clocking scheme, each logic stage is only given one half of a clock cycle to evaluate anyway. So while one block is evaluating, another is pre- chargingandviceversa,ascanbeseeninFigure1.4[7]. Thereareotherwaysofusingprechargelogic,asdescribedinRef.[3].Inthiscase, staticandprechargelogicsareinterleavedandstaticlogicpropagatessignalswhilepre- chargelogicisbeingprecharged.Inthisway,thereisstillsignalpropagationonevery phase.Thisapproachisacompromisebetweenusingstaticandprechargelogics. There are times when precharge logic is not faster than static. With latch-based clocking schemes, static logic can take advantage of “time borrowing” [7], which mayresultinbettertimingthanprechargelogic.Timeborrowingsimplymeansthat signals can flow to the next block of logic without having to wait for a clock edge. Thus, the next block starts evaluating early, in a way “borrowing” time from the currentblock.Butprechargegatescansometimestakeadvantageoftimeborrowing. 4 SynchronousPrechargeLogic Φ Φ Φ Φ Φ Logic Logic Figure1.4 Prechargelogicwithlatches. If the logic stages on both sides of a latch consist of precharge logic, then time bor- rowing is possible [7]. This is done by overlapping the evaluation phases of both stages. We will discuss this in detail in Chapter 2. Furthermore, the use of a dual monotonic(dualrail,precharged)latchalsoremovesthesynchronizationpointthatis createdbetweenlatchesandprechargelogicblocks[4].Itisthereforeclearthatthere are numerous ways to overcome synchronization point problems in precharge logic. Aswithotherlogicfamilies,alogicchainislimitedbythedurationoftheevaluation phase.Alloutputsmustbestoredatthepointthatthelatchontheoutputcloses. Letusnowsummarizethefactorsthatimpactthespeedofprechargelogic: (cid:1) nofightingbetweenPMOSandNMOStrees, (cid:1) evaluationstartsassoonaswereachVtnoftheNMOSdevice, (cid:1) lowerinputcapacitanceforthesameoutputcurrent, (cid:1) invertingstaticgatecanbeskewedinfavorofthecriticaledge. 1.4 Advantages of Precharge Logic There are a number of advantages to using precharge logic. As mentioned above, prechargelogicisfasterthanstaticlogicduetoseveralfactors.Inaddition,thepre- charge logic gates are smaller in physical size because there is only a single PMOS pullup device. Of course, this only holds true when implementing Boolean func- tions that are more complicated than a simple inverter. Not having to implement a full PMOS tree can thus result in large savings in areas in logic gates with a large fan. The reason for this is that the carrier mobility in PMOS devices is lower than that of NMOS devices. This condition requires the use of significantly larger PMOS devices to achieve the same resulting conductivity as that of the smaller NMOS devices. In addition to the area penalty for the larger PMOS devices, a per- formance penalty will be paid for their use due to self-loading and input loading. Self-loading comes from the fact that any increase in the node capacitance on the output of a logic gate will reduce its performance. So as we increase the width of a transistor, its associated parasitic capacitance increases as well. The reduction to self-loading (as compared to static circuits) allows the efficient construction of gatessuchasan8inputmultiplexerorNORgate. PrechargeLogicBasics 5 Because the precharge logic gates are smaller, the gates thatdrivethem can also be smaller. Naturally, this is because the precharged gates present a smaller load capacitance to their drivers. The other way to look at this is that the driving gates can be faster, if not reduced in size. Not reducing the driver size may not be the best choice; however, a fanout of 3 to 4 is known to be optimum for most applica- tions.Furthermore,largergates may stillnotbeable tocompensate forwire RC, as shown in Figure 1.5. If there are two resistors in series, the total resistance can neverbesmallerthananyoneoftheresistors. So far it was established that precharged gates are faster because there is no fightingbetweenthepullupandpulldownnetworks.Italsowaspointedoutthatthe pulldown time is not improved as much as the pullup time because there is still a full NMOS tree of transistors and there is an additional NMOS device placed in series with the tree. But as we will learn in Section 1.6, just about all precharged gatesare followed byastaticinverter, asshowninFigure1.6,which happenstobe a NOR gate. While this will be discussed in detail in Section 1.6, it is worth point- ing out that with the static inverter, the whole logic gate can evaluate faster, even with the additional propagation delay from the inverter. This is due to the fact that now there are not any series transistor stacks driving the next gate, there is only an inverter with a single PMOS and NMOS device, driving the load with an inverter is potentially the fastest one can get in a given technology. In order for the inverter to provide such improvement in speed, its PMOS device should be sized much larger than its NMOS device. However, this severely reduces the noise margin. In RW RW 0 R R T = R + R N N TOT N W = R W Figure1.5 Transistordrivingawireload. Figure1.6 PrechargedNORgatewithastatic inverterbecomesanORgate. Clock Output Clock 6 SynchronousPrechargeLogic fact, some people increase the NMOS device to improve the noise margin at the expense of speed. If a circuit is designed to be fast but it does not work on actual silicon, then it is useless. Improvements to the noise margin will be discussed in Chapter4. Precharge logic gates are inherently less noisy because there is no short circuit (crowbar) current flowing from power to ground during each transition. The crow- bar current is such that it has a large initial spike and a gradual rolloff, rather than amoremoderateandconstantlevel.Thisspikeofcrowbarcurrenthasthetendency tocauselocalpowersupplydeviations.Thisisnormally thesourceofΔInoise.As less current flows, there is also less power dissipation in the logic gate. There is also less power dissipation at the input to the logic gate because the input capaci- tance is smaller. However, because the clock must be routed to many more places on the chip, there is increased power dissipation in the clock wires. Furthermore, if an input to a precharged gate is not switching, the output might switch with the clock, which increases overall power dissipation. Therefore, it is not clear what the impact on power dissipation is, and this has to be addressed on a case-by-case basis. Another advantage of precharge logic design is that these circuits allow the designer to optimize the transistors for one edge of interest. This is in direct con- trast to static circuits that will need to make their rising and falling output edge ratesnearlyequal. Yet another advantage to precharge logic design is that these circuits can be expanded to include a latch mechanism in the logic circuitry without significantly slowing down the circuit. This is discussed in detail in Chapter 2 and also in Chapter7. A final advantage to precharge (domino) gates is that any resulting circuit will be glitch-free by construction. This is due to its single transition nature. As we will learninSection 1.6,the onlytransitionthatadominocircuitcan makeduringeval- uationisthatofazerotoonetransition,ontheoutputofthecircuit. Itisnowworthwhiletosummarizetheadvantagesandalsomentionafewdisad- vantagesofprechargelogic. Advantages: (cid:1) Fasterswitching (cid:1) Lessnoiseproduced (cid:1) Lesspowerdissipation(potentially) (cid:1) Smallergateinputcapacitance (cid:1) Smallerlayoutarea (cid:1) Optimizedforoneedgeofinterest (cid:1) Integratedlatchmechanismpossible (cid:1) Glitch-freebyconstruction(domino) (cid:1) Greatforhighfan-ingates. Disadvantages: (cid:1) Lowernoisemargin (cid:1) Difficultywith“timeborrowing” PrechargeLogicBasics 7 (cid:1) Lackofinversions(domino) (cid:1) Theneedtoroutetheclocktoallgates (cid:1) Trickydesign(chargesharingandleakageondynamicnodes) (cid:1) Morepowerdissipation(potentially) (cid:1) Difficulttointerfacewith,requiremonotonicsignals(domino) (cid:1) Requireaprechargephasetopreparethemforthenextlogicevaluation (cid:1) Minimumfrequencyofoperation—cannotholdstateinstaticmode. In addition, it should be noted that precharge logic is a ratioless logic family, meaning that the slope of the transfer characteristic is not dependent on the ratio of thesizesofthePMOSandNMOStransistors. 1.5 What About Using Other Transistors? Precharge logic can only be realized with MOS transistors. In order for a node to retain its charge for a reasonable amount of time, all leakage currents must be very small. When using MOS transistors, the leakage currents can be indeed small (though in modern processes leakage has increased considerably). In any case, compared to other transistor types, the enhancement mode MOS transistor can be fully turned off, thus lowering leakage. Other technologies based on devices such as bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), metal semiconductor field effect transistors (MESFETs), high electron mobility transistors (HEMTs), depletion mode MOSFETs, etc., in general, all have leakage currents too high to retain charge on the dynamic node. Furthermore, the MOS transistors have a good insulator between the gate and the channel, i.e., the gate oxide. This also helps to retain the charge, because the charge does not really get stored on the output of a logic gate, but on the next gate’s input. Dynamic storage is a major advantage of MOS devices, though in modern technologies the oxide is very thin and there is more leakage through the oxide. To keep the drain current reasonable and also to prevent the oxide from getting too thin, a high “k” dielectric isusedinmodernprocesses[26]. 1.6 Domino Logic Dominologic isaspecial versionofprechargelogic,whichhasacertainrestriction on the signals flowing from logic gate to logic gate. The restriction is that all sig- nalsontheinputsofaprechargedlogicgate,intheevaluationphase,canonlytran- sition from LOW to HIGH, or remain LOW. These types of signals are referred to as monotonically rising, because they can only make one transition, from LOW to HIGH (in the evaluation phase). The word “monotonic” means “changing in one directiononly”[4]. 8 SynchronousPrechargeLogic Logic expects a transition back to HIGH Output Input but circuit cannot recover Clock Illegal input transition Figure1.7 Dischargeofanoutputnodeduetoanillegalinputtransitioninanevaluation phase. 1.6.1 Need for Monotonic Signals PrechargedgatessuchastheoneshowninFigure1.1cannotbecascadedinasimple manner. Thesegates require that all inputs bestable before the start ofanevaluation phase of a gate, or be monotonically rising after the evaluation phase has started. So if we had a block of logic, each logic gate would have to have a separate clock to ensure that each gate is precharged when its inputs are unstable. This is ridiculous both because of the enormously complicated clocking scheme it would require and becausepropagationdelaysvaryfromlogicblocktologicblock.Butifthiscondition isnotmet,simpleprechargedlogicgatescannotbecascaded[6]. If precharged logic gates are to be cascaded, limitations must be put on the sig- nals that flow from gate to gate. If a gate started evaluating a signal that bounced around between power and ground, the precharged gate would be discharged with- outpossiblerecovery.Or,ifasignal started outHIGH andsettled down toaLOW, then the output we want is a HIGH. But the output was discharged by the input startingHIGH(assumingevaluationphase,ofcourse),creatingapathfromtheout- put to V , as can be seen in Figure 1.7. Once the input settles to a LOW, there is ss nothing to restore the output and it will remain LOW. So this is why all signals shouldstartLOW,andatmostmakeonetransitionfromLOWtoHIGH[6]. 1.6.2 Domino Logic Gates The modification to existing precharged logic gates is simple. All that is needed is theadditionofastaticinvertinggateontheoutputoftheprechargedlogicgate[12]. ThisisshowninFigure1.8.Adominogateactuallyreferstotwostages,ratherthan asinglegate.Inanycase,inthiswayablockoflogicgatescanbeprechargedwith thesameclock.So,whenalogicgateisprecharged,thedynamicnodeisprecharged HIGH,buttheoutputofthestaticgateisLOW.Thus,allinputstoprechargedgates start out LOW in an evaluation phase, as desired. Another way to state this is that PrechargeLogicBasics 9 Figure1.8 Standarddominogate. Clock N Clock Inverter guarantees monotonically rising input here Clock f r f r r N N Need stable inputs here Figure1.9 Chainoftwodominologicgates. thedynamicnodeismonotonicallyfalling,andtheoutputofthestaticinvertinggate is monotonically rising. So by combining each precharged gate with a static invert- inggate,theoutputisavalidsignalintoanotherprechargedlogicgate[4]. A queue of domino blocks can fall, but cannot get up by itself. Similarly, a pre- charged logic gate’s output can only fall (NMOS) when it evaluates [4]. So a chain of gates looks like a queue of domino blocks. In Figure 1.9, “r” means signals are monotonically rising and “f” means signals are monotonically falling. The output of a domino gate starts LOW. It either stays LOW, or it raises HIGH. If it does not change, then the next domino gate is unaffected. But if it rises, then the next dom- ino gate might transition its output from LOW to HIGH, depending on other inputs to that domino gate. As already discussed above, the static inverting gate (inverter in most cases) improves the noise margin and improves speed, because one device (asopposedtoaseriesstackoftransistors)drivesthenextgate. The problem with domino logic is that it is noninverting. Thus, not all functions canbeimplementedwithdominologic. 10 SynchronousPrechargeLogic 1.7 Keepers: Improving the Charge Storage Precharge logic is in many cases dynamic logic, in the sense that its outputs are dynamic nodes. Sometimes there may be problems with charge storage due to excessive leakage in the circuit. “Keepers” may be used to replenish the lost charge. A keeper is a small (weak) PMOS device connected to the dynamic node and driven by a static inverter, as shown in Figure 1.10. This circuit restores the chargelostonthedynamicnode. Another example of using a keeper is shown in Figure 1.11. Here, a keeper is used on a Svensson style latch [5]. The dynamic node is the node in the middle of the circuit, marked “x.” The reason for the node being dynamic is due to the fact that when the latch is closed (enable is LOW) and the input is HIGH, node “x” is floating. We only care about the case when this node is HIGH, because if it is LOW and drifts up in potential, there will not be any unwanted transitions. Keeper Figure1.10 Useofa“Keeper”tomaintain chargeonthedynamicnode. Clock N Clock Keeper Figure1.11 Svenssonstylelatchwitha “Keeper.” D x Q Enable