JOURNALOFLATEXCLASSFILES,VOL.14,NO.8,AUGUST2015 1 Subnanosecond Time-to-Digital Converter Implemented in a Kintex-7 FPGA Yuta Sano, Yasuyuki Horii, Masahiro Ikeno, Osamu Sasaki, Makoto Tomoto, and Tomohisa Uchida 7 1 Abstract—Time-to-digital converters (TDCs) are used in var- In this study, an eight-channel TDC with a variable bin 0 ious fields, including high-energy physics. One advantage of size down to 0.28 ns is implemented and tested in a Xilinx 2 implementingTDCsinfield-programmablegatearrays(FPGAs) Kintex-7 FPGA [5]. The FPGA is XC7K325T-2FFG900 and n iusnleoxgpieccstecdanprboeblflemexsibalnydmchoadnifigeeds,inwthhiechexipseruismefeunltatolccoonpdeitiwonitsh. hasa speed gradeof -2.Thisstudy extendsthe demonstration a Recent moderate FPGAs make it possible to implement TDCs describedin [6] by further analysingand interpretingthe data J withasubnanosecondbinsize.Hereinaneight-channelTDCwith aswellasmeasuringthepowerconsumption.Additionally,the 9 a variable binsizedown to0.28 nsisimplementedand tested in potentialtoextendthenumberofchannelsto256isdiscussed. 1 a Xilinx Kintex-7 FPGA. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external ] reference clock. Calibration of the bin size is unnecessary if a II. DESIGN OF THETDC t e stable reference clock is available, which is common in high- Fig. 1 shows a block diagram of the TDC, which was d energy physics experiments. Depending on the channel, the designed to measure the timing of both the leading and the - standard deviation of the differential nonlinearity for a 0.28-ns s binsize is 0.06–0.14 and thetime resolution is0.08–0.10 ns. The trailing edges of the input signal. The fine time measurement n performance has a negligible dependence on the temperature. isbasedonfree-runningcounters(‘finetimecounters’),which i . Power consumption and the potential to extend the number of are designed with a multisampling scheme and quad phase s channels are also discussed. c clocks[7],[8],[9].Eachquadphaseclockhasafrequencyone si IndexTerms—Fieldprogrammablegatearrays,Time-to-digital quarter of the fine time counters. The quad phase clocks are y converter. produced from an external reference clock at the clock man- h ager integrated in the Kintex-7 FPGA, where the supported p [ I. INTRODUCTION maximumfrequencyis933MHz.Anexternalreferenceclock TIME-TO-DIGITALconverters(TDCs)areusedinvarious with a 110 MHz frequency corresponds to that of the quad 1 phase clocks of 880 MHz and a 0.28-ns bin size. v fields, including high-energy physics. For example, in The difference in the lengths of the divided input signal 5 the ATLASexperiment[1], themuonmomentumismeasured paths (see Fig. 1) is crucial for the TDC performance.In this 7 withmonitoreddrifttubechambersbasedonTDCswithabin 3 size of 0.78ns, whichareimplementedin application-specific study, the locations of the first four D-type flip-flops in each 5 channelwere constrained so that they are close to each other. integrated circuits [2]. Moderate field-programmable gate ar- 0 Thedatafromthefinetimecounterincludesathree-bittime rays(FPGAs)makeimplementingTDCswithananosecondor . 1 count and a one-bit identifier of the leading and the trailing small bin size possible [3], [4]. In manycases, the bin size of 0 edges.Thesedataarecombinedwiththedatafromafourteen- TDCs basedon the propagationdelaytime mustbe calibrated 7 bit coarse time counter, and stored in a channel buffer. The 1 to cope with the delay time dependence on the temperature channel buffers for all channels are scanned, and the data is : as well as the location and routes of the delay units. On the v transferred to a buffer with a five-bit channel identifier. Then otherhand,the TDCs in thisstudy,whichare based onmulti- i X phase clocks managed by a highly reliable clock manager thedataarereadoutonebyone.Thedynamicrangefora bin size of 0.28 ns is 37 µs. The dynamic range can be extended r integrated in the FPGA, do not require bin size calibration. a by changing the number of bits for the coarse time counter. Implementation of TDCs in FPGAs provides flexibility be- causelogicscanbemodifiedtodealwithunexpectedproblems and changes in the experimental conditions. Data transfer at III. DEMONSTRATORAND TESTSETUP a rate of gigabits per second can be handled with the robust Fig.2showsapictureofthedemonstrator,whichconsistsof transceivers integrated in FPGAs. a motherboardand a daughtercard. The motherboardis com- patible with the versatile backplane bus standard VME [10]. Manuscript submitted to IEEE Transactions on Nuclear Science. (Corre- It has a Kintex-7 FPGA (type is XC7K325T-2FFG900). Al- spondingauthor:Y.Horii.) Y. Sano and Y. Horii are with the Graduate School of Science, thougheitheranonboard40-MHzquartzoscillatororaLEMO Nagoya University, Nagoya, Japan (e-mail: [email protected] coaxialconnector[11]canprovidethesystemclock,thisstudy [email protected]).M.TomotoiswiththeGraduateSchool employed the latter. Additionally, the output from the FPGA ofScienceandtheKobayashi-MaskawaInstitute,NagoyaUniversity,Nagoya, Japan (e-mail: [email protected]). M. Ikeno, O. Sasaki, and canbereadthroughthebackplaneoragigabitEthernetwitha T. Uchida are with the Institute of Particle and Nuclear Studies, High Transmission Control Protocol processor implemented in the Energy Accelerator Research Organization (KEK), Tsukuba, Japan (e-mail: FPGA(SiTCP)[12],butthelatterwasused.Thedaughtercard [email protected], [email protected], [email protected]). ThisworkwassupportedbyJSPSKAKENHIGrantNumberJP23104005. haseightLEMOcoaxialconnectorsassignalinputs.Theinput JOURNALOFLATEXCLASSFILES,VOL.14,NO.8,AUGUST2015 2 440 MHz Coarse time where i (i = 0, 1, 2, ...) is the bin index, ti is the bin size forbini,andt isthedesignedbinsize.ToevaluateD ,the bin i time difference of the leading edges between the signal and external reference clocks was measured. Multiple bins were Fine time annel buffer Buffer iaAnnvdpeesertxiiogtedartinecdaslbtrryuecfsetcuraernenncwienigtchltohacekctsyimcwleeitdhoiffaffeo3reu3nr-cpbesinbssetetwwpaesseiznfeotuh(neFdisg.ig.Tn3ha)el. Ch maximum magnitude of the measured Di is 0.6. The delay ∆ before the first D-type flip-flop for each j 270˚ 180˚ 90˚ 0˚ divided input signal path j (j = 0, 1, 2, 3) was estimated 880 MHz quad phase clocks 440 MHz 110 MHz by a Xilinx Vivadodesign tool.Based on the estimated delay, the bin size t for each quad clock phase j was calculated as j Fig. 1. Block diagram of the TDC. The signal path is divided into four, and the signal time is detected by the D-type flip-flops based on the four t =t +∆ −∆ . (2) j bin j j+1 differentclockphases.ThelocationsofthefourleftmostD-typeflip-flopsare constrained to control the difference between the divided signal paths. Each Acyclicrelationof∆ =∆ wasusedtocalculatet .TableI channel hasacircuit, whichisinsidethesquarewiththedashedline. 4 0 3 shows the measured and calculated bin sizes for a channel. Fig. 4 shows the distribution of the difference between the compatiblewiththeNIMfastnegativesignal[13]isconverted measuredandcalculatedbinsizesforall32quadclockphases into a 3.3 V LVCMOS signal [14] with Texas Instruments of the 8 channels. The difference is O(0.01) ns, implyingthat SN65LVDS348PW [15]. Then the signal is transferred to the the main source of the periodic structure in Fig. 3 is the FPGA on the motherboard. difference in the divided input signal paths. The signal and externalreferenceclocksare fromthe pulse Asachannel-levelmeasureofD ,thedeviationσisdefined i generator Agilent 81150A [16]. The standard deviation of for each channel by the time difference between the leading edges of the two N−1 spyenrfcohrrmonanisceedspouflsbeisnfsriozmestohfe0p.u7l8sensg,en0e.3r9atonrs,isan3d00p.s2.8Tnhse, σ2 = N1 X Di2, (3) i=0 which correspond to the external reference clock frequencies of 40 MHz, 80 MHz, and 110 MHz, respectively, were where N is the total number of bins. Fig. 5 shows the result evaluated.Unless otherwisespecified,the resultsforthe 0.28- of the measurement of σ. The obtained value, which varies ns bin size are shown. Although the leading edges were between 0.06–0.14, depends on the channel. evaluated, the trailing edges should produce similar results since common clocks and D-type flip-flops are used. TABLEI RELATIONBETWEENTHECALCULATEDANDTHEMEASUREDBINSIZES. Phasej Inputsignal Calculated Measured delay∆j [ns] binsize[ns] binsize[ns] 0 4.62 0.20 0.21 1 4.70 0.20 0.20 2 4.79 0.34 0.36 3 4.73 0.39 0.37 16 PHY 14 s in 12 B f 10 o r 8 e Ref. clock Output (RJ45) Input b m 6 u N 4 Fig.2. Pictureofthedemonstrator. 2 0 -0.1 -0.05 0 0.05 0.1 IV. DIFFERENTIALNONLINEARITY Bin Size Difference (ns) The differential nonlinearity D is defined by i t −t Fig.4. Difference between themeasuredandcalculated binsizes. i bin D = , (1) i t bin JOURNALOFLATEXCLASSFILES,VOL.14,NO.8,AUGUST2015 3 Di 0.6 Di 0.6 y y rit 0.4 rit 0.4 a a e e n 0.2 n 0.2 nli nli No 0 No 0 al -0.2 al -0.2 nti nti re -0.4 re -0.4 e e f f Dif -0.6 Dif -0.6 0 10 20 30 40 50 60 0 10 20 30 40 50 60 Bin Index i Bin Index i (a) Differential nonlinearity Di forchannel 1. (b) Differential nonlinearity Di forchannel 2. Di 0.6 Di 0.6 y y rit 0.4 rit 0.4 a a e e n 0.2 n 0.2 nli nli No 0 No 0 al -0.2 al -0.2 nti nti re -0.4 re -0.4 e e f f Dif -0.6 Dif -0.6 0 10 20 30 40 50 60 0 10 20 30 40 50 60 Bin Index i Bin Index i (c) Differential nonlinearity Di forchannel 3. (d) Differential nonlinearity Di forchannel 4. Di 0.6 Di 0.6 y y rit 0.4 rit 0.4 a a e e n 0.2 n 0.2 nli nli No 0 No 0 al -0.2 al -0.2 nti nti re -0.4 re -0.4 e e f f Dif -0.6 Dif -0.6 0 10 20 30 40 50 60 0 10 20 30 40 50 60 Bin Index i Bin Index i (e) Differential nonlinearity Di forchannel 5. (f) Differential nonlinearity Di forchannel 6. Di 0.6 Di 0.6 y y rit 0.4 rit 0.4 a a e e n 0.2 n 0.2 nli nli No 0 No 0 al -0.2 al -0.2 nti nti re -0.4 re -0.4 e e f f Dif -0.6 Dif -0.6 0 10 20 30 40 50 60 0 10 20 30 40 50 60 Bin Index i Bin Index i (g) Differential nonlinearity Di forchannel7. (h) Differential nonlinearity Di forchannel 8. Fig.3. Resultofthemeasurementofthedifferential nonlinearity Di. JOURNALOFLATEXCLASSFILES,VOL.14,NO.8,AUGUST2015 4 0.5 300 0.4 250 σ n 0.3 s 200 o e viati 0.2 Entri 150 De 100 0.1 50 0 0 1 2 3 4 5 6 7 8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 Channel Difference between Input and Output (ns) (a) Fig.5. Deviation σ ofthedifferential nonlinearity. 0.115 V. INTEGRALNONLINEARITY ) 0.11 s n The integral nonlinearity I is given by ( 0.105 n o T −T i 0.1 I = (cid:10) measured(cid:11) input, (4) ut t ol 0.095 bin s where T is the time differencebetween the leadingedges Re 0.09 input of the input signal clock and (cid:10)Tmeasured(cid:11) is the mean of the me 0.085 measurements. The time difference was scanned up to 37 µs, Ti 0.08 and T is obtained for each time difference from (cid:10) measured(cid:11) 0.075 8500 measurements. The value of I is consistent with zero 1 2 3 4 5 6 7 8 in the full range of the measurement, and the graph is fitted Channel by a linear function I = A·T +B. The fit results are input shown in Fig. 6. The uncertainty of the slope parameter A (b) corresponds to 1 ps over 37 µs. Fig.7. (a)Distributionofthedifferencebetweenthemeasuredandinputtime difference. (b) Time resolution by channel. Line indicates the quantisation VI. TIME RESOLUTION error. The time resolution was evaluated using data with various valuesofthetimedifferencebetweentheleadingedgesofthe VIII. POWERCONSUMPTION input signal clock. Specifically, the standard deviation of the The power consumption of FPGA for the eight-channel difference between the measured and input time differences TDC was estimated by the Vivado design tool. Table II sum- was examined (Fig. 7). The obtained value depends on the marisestheresultsof28◦Cand68◦Cforbinsizesof0.28ns channelandranges0.08–0.10ns.Theresultisfullycorrelated and0.78ns.Thedominantcontributorsforthedynamicpower with the deviation σ, as seen by comparing Fig. 7 (b) and consumption are found to be the clock manager and SiTCP, Fig.5.Thetimeresolutiondependsonthedifferencebetween which spend about 40% and 30%, respectively. The power the input signal paths. For larger bin sizes, the effect of consumption for one-channel TDC was also estimated. As- the difference between the input signal paths relative to the suming a linear relation between the number of channels and quantisation error becomes smaller. the power consumption, the power consumption per channel forthebinsizesof0.28nsand0.78nsis0.02Wand0.01W, VII. TEMPERATUREDEPENDENCE respectively. The temperature dependences of D and I were evalu- Fig. 9 shows the measured power consumption of the i ated with a thermostat chamber ESPEC SH-641 [17] for a demonstrator.The measurementwas performedwith the ther- temperature range from −10 ◦C to 60 ◦C. The data were mostat chamber ESPEC SH-641 in a range from −10 ◦C acquiredafter the temperatureof FPGA became stable during to 60 ◦C. The temperature of the FPGA during the mea- the operation. The temperature of FPGA during operation is surement is about 8 ◦C higher than that of the chamber. about 8 ◦C higher than that of the chamber. Fig. 8 (a) shows The measured power consumption for the 0.28-ns bin size therelationbetweenthedeviationσofD andthetemperature. at a chamber temperature 20 ◦C is 4.1 W. The static power i Fig. 8 (b) shows the relation between the slope parameter A consumption of the demonstrator for the same bin size from the linear fit to I and the temperature. The temperature and temperature measured without firmware implemented in dependence is small in the investigated temperature range. FPGA is 2.0 W. The dynamic power consumption of Texas JOURNALOFLATEXCLASSFILES,VOL.14,NO.8,AUGUST2015 5 I A = (-0.1 ± 2.6) × 10-9 [/ns] I A = (4.2 ± 2.3) × 10-9 [/ns] y 0.002 y 0.002 rit B = (1.8 ± 3.2) × 10-5 rit B = (-7.6 ± 2.9) × 10-5 a a e e n n nli 0 nli 0 o o N N al al r r g g e e nt-0.002 nt-0.002 I I 103 104 103 104 Input Time Differece (ns) Input Time Differece (ns) (a) Integral nonlinearity I forchannel 1. (b) Integral nonlinearity I forchannel 2. I A = (-0.9 ± 2.5) × 10-9 [/ns] I A = (5.4 ± 2.6) × 10-9 [/ns] y 0.002 y 0.002 rit B = (-5.9 ± 2.9) × 10-5 rit B = (-9.5 ± 3.3) × 10-5 a a e e n n nli 0 nli 0 o o N N al al r r g g e e nt-0.002 nt-0.002 I I 103 104 103 104 Input Time Differece (ns) Input Time Differece (ns) (c) Integral nonlinearity I forchannel 3. (d) Integral nonlinearity I forchannel 4. I A = (0.5 ± 2.7) × 10-9 [/ns] I A = (5.1 ± 2.5) × 10-9 [/ns] y 0.002 y 0.002 rit B = (-3.0 ± 3.3) × 10-5 rit B = (-11.5 ± 3.1) × 10-5 a a e e n n nli 0 nli 0 o o N N al al r r g g e e nt-0.002 nt-0.002 I I 103 104 103 104 Input Time Differece (ns) Input Time Differece (ns) (e) Integral nonlinearity I forchannel 5. (f) Integralnonlinearity I forchannel 6. I A = (2.2 ± 2.5) × 10-9 [/ns] I A = (3.5 ± 2.6) × 10-9 [/ns] y 0.002 y 0.002 rit B = (-9.6 ± 2.9) × 10-5 rit B = (-8.8 ± 3.1) × 10-5 a a e e n n nli 0 nli 0 o o N N al al r r g g e e nt-0.002 nt-0.002 I I 103 104 103 104 Input Time Differece (ns) Input Time Differece (ns) (g) Integral nonlinearity I forchannel 7. (h) Integral nonlinearity I forchannel 8. Fig.6. Resultofthemeasurementoftheintegralnonlinearity I.CurvesshowtheresultsofalinearfitbyI =A·Tinput+B.Fittedvaluesofparameters AandB arealsoshownforeachplot. JOURNALOFLATEXCLASSFILES,VOL.14,NO.8,AUGUST2015 6 4.6 ) W 0.5 Bin size: 0.28 ns Bin size: 0.28 ns ( Bin size: 0.39 ns on 4.4 Bin size: 0.39 ns σ 0.4 ti n Bin size: 0.78 ns mp Bin size: 0.78 ns o 4.2 viati 0.3 onsu De 0.2 r C 4 e w 0.1 Po 3.8 -10 0 10 20 30 40 50 60 -10 0 10 20 30 40 50 60 Temperature of Thermostat Chamber (°C) Temperature of Thermostat Chamber (°C) (a) Fig.9. Measured powerconsumption ofthe demonstrator during operation. Circle,square,andtriangleplotscorrespondtobinsizesof0.28ns,0.39ns, ×10-6 0.5 and0.78ns,respectively. 0.4 ) 0.3 s To discuss the extension of the number of channels, we n / 0.2 ( developedfirmwarewith256channelsandcheckedtheutilised A 0.1 lt 0 resources (Table IV). The ratio of the utilised input/output u portstothetotalinput/outputportsis58%,whiletheratiosfor s -0.1 Re the other elements are smaller. The difference in the divided -0.2 t input signal delay for each channel was evaluated by the Fi -0.3 Vivadodesign tool. The standarddeviationof the inputsignal -0.4 delay is 0.14 ns, indicating that the performance of the 256- -0.5 -10 0 10 20 30 40 50 60 channelTDCshouldbesimilartotheoneoftheeight-channel Temperature of Thermostat Chamber (°C) TDCdemonstratedinthisstudy.Theclockskewmayaffectthe offsetbetweenthe channels,butitiswithina rangesupported (b) for the employed Kintex-7 FPGA. Fig. 8. (a) Temperature dependence on the deviation σ of the differential nonlinearity for channel 8. Circle, square, and triangle plots correspond to TABLEIII binsizesof0.28ns,0.39ns,and0.78ns,respectively.(b)Slopeofthelinear UTILISATIONOFTHEFPGARESOURCESFOREIGHT-CHANNELTDC. fitfortheintegral nonlinearity forchannel 8andabinsizeof0.28ns. Resource Utilisation Available Ratio[%] Look-uptables 4361 203800 2.1 Instruments DP83865DVH [15] for Ethernet data transfer, Registers 5939 407600 1.5 which is considered the main consumer on the demonstrator Memory 48 445 10.8 Input/output ports 60 582 10.3 other than FPGA, is estimated to be 1.3 W. The value of Clocking 14 32 43.8 4.1 W −(2.0 W+1.3 W) = 0.8 W is close to the value estimated from the Vivado design tool of 0.73 W. TABLEIV TABLEII UTILISATIONOFTHEFPGARESOURCESFOR256-CHANNELTDC. POWERCONSUMPTIONESTIMATEDBYTHEXILINXDESIGNTOOL. Resource Utilisation Available Ratio[%] Binsize[ns] Temp.[◦C] Dynamic[W] Static [W] Total[W] Look-uptables 27682 203800 13.6 0.28 28 0.56 0.18 0.73 Registers 48826 407600 12.0 0.28 68 0.56 0.59 1.15 Memory 180 445 40.4 0.78 28 0.43 0.18 0.61 Input/output ports 292 582 58.4 0.78 68 0.43 0.59 1.02 Clocking 14 32 43.8 IX. RESOURCES AND NUMBER OF CHANNELS X. CONCLUSION Table III summarises the utilisation of the FPGA resources An eight-channel TDC with a variable bin size down to for the tested eight-channel TDC. Because multiple clocks 0.28 ns was implemented and tested in a Xilinx Kintex-7 with different frequencies are generated, the ratio of the FPGA. The TDC is based on a multisampling scheme with utilisedclockresourcestothetotalclockresourcesisrelatively quad phase clocks synchronised with an external reference large.Mostoftheresourcesofthelook-uptables,theregisters, clock. The measured time resolution for a 0.28-ns bin size is and the random-access memory are spent by SiTCP. 0.08–0.10ns,dependingonthechannel.Theperformancehas JOURNALOFLATEXCLASSFILES,VOL.14,NO.8,AUGUST2015 7 a negligible dependence on the temperature. The number of channelscan be increasedupto hundredsof channelswithout significantly changing the TDC performance. Implementationof TDCs in FPGAs increasesthe flexibility tomodifylogics.Thisfeatureisextremelyadvantageouswhen copingwithunexpectedproblemsorchangesintheexperimen- talconditions.Ifastablereferenceclockisavailablesuchasin high-energy physics experiments, the TDC in this study does not need to be calibrated. Consequently, FPGA-based TDCs should be useful in fields requiring subnanosecond resolution and multiple channels. ACKNOWLEDGMENT We acknowledge the support of the demonstrator develop- pers Hiroshi Sakamoto, Chikuma Kato, Takayuki Tokunaga, andYusakuUrano,atTheUniversityofTokyo,Tokyo,Japan. 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