STRUCTURED ELECTRONIC DESIGN This page intentionally left blank Structured Electronic Design Negative-feedback amplifiers by C.J.M. Verhoeven Delft University of Technology, Delft, The Netherlands A. van Staveren Delft University of Technology, Delft, The Netherlands G.L.E. Monna SystemtematIC Design B.V., Delft, The Netherlands M.H.L. Kouwenhoven National Semiconductor Corporation, Delft, The Netherlands and E. Yildiz Delft University of Technology, Delft, The Netherlands KLUWER ACADEMIC PUBLISHERS NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW eBookISBN: 0-306-48732-2 Print ISBN: 1-4020-7590-1 ©2004 Springer Science + Business Media, Inc. Print ©2003 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook maybe reproducedor transmitted inanyform or byanymeans,electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Springer's eBookstore at: http://www.ebooks.kluweronline.com and the Springer Global Website Online at: http://www.springeronline.com Contents Preface xiii 1. INTRODUCTION TO STRUCTURED ELECTRONIC DESIGN 1 1.1 Searching the “circuit space” 1 1.2 Circuit performance 3 1.2.1 Fundamental specifications 4 1.3 Fast synthesis 5 1.3.1 Orthogonality 5 1.3.2 Model simplification 7 1.3.3 Hierarchy 7 1.3.4 Summary 8 1.4 Synthesis of electronic circuits 8 1.4.1 Implementation limitations 9 1.4.2 Specifications 11 1.5 Small-signal models, biasing and distortion 13 1.5.1 Models 13 1.5.2 Biasing 14 1.5.3 Distortion 17 1.5.4 Checking device parameters 18 1.6 The chain matrix 21 1.6.1 Chain matrices of devices 22 1.7 Exercises 24 2. SYNTHESIS OF ACCURATE AMPLIFIERS 27 2.1 Introduction 27 2.2 The definition of an amplifier 29 2.2.1 Configurations for high-performance amplifiers 29 v vi CONTENTS 2.2.2 The nullor 32 2.3 The asymptotic-gain model 34 2.4 The synthesis of 35 2.4.1 Step 1: The determination of the input and output quantities 35 2.4.2 Step 2: The synthesis of the feedback network 37 2.5 The next steps: Synthesis of the nullor 39 2.6 Topology synthesis of the nullor 40 2.6.1 The cascade topology 40 2.6.2 Two-ports with active devices 41 2.6.3 Replacing the nullator and the norator 43 2.6.4 The ideal substitution and the practical situation 44 2.6.5 The current mirror as a stage in the nullorcircuit 47 2.7 Step 3: Design of the first nullor stage: noise 49 2.8 Step 4: Design of the last nullorstage: distortion 50 2.9 Step 5: Bandwidthoptimization 51 2.9.1 Bandwidth estimation 51 2.9.2 The actual frequency compensation 53 2.9.3 Model refinement 53 2.10 Step 6: Biasing 54 2.11 A note on current conveyors 56 2.12 Exercises 58 3. NEGATIVE FEEDBACK 67 3.1 Introduction 67 3.2 Accurate transfer 68 3.2.1 Negative feedback 68 3.2.2 Adaptation to source and load 68 3.3 The Asymptotic-Gain model 69 3.4 Transfer of an amplifier 72 3.5 Nullor feedback networks 72 3.6 Feedback networks 73 3.6.1 Transformer and gyrator networks 73 3.6.2 Passive single-loop feedback by one port elements 74 3.6.3 Indirect feedback 75 3.6.4 Active feedback 75 3.7 Example: asymptotic-gain model 76 vii 3.8 Exercises 80 4. NOISE 85 4.1 Measure for the Amplifier Noise Performance 86 4.1.1 Signal-to-Noise Ratio 86 4.1.2 Equivalent Input and Output Signal-to-Noise Ratio 87 4.1.3 Available Input Signal-to-Noise Ratio 88 4.1.4 Summary 91 4.2 Equivalent Input Noise Source 91 4.2.1 The Equivalent Input Noise Source 92 4.2.2 Transform-I: Voltage Source Shift 93 4.2.3 Transform-II: Current Source Shift 94 4.2.4 Transform-III: Norton-Thevenin Transform 95 4.2.5 Transform-IV: Shiftthrough Two-ports 96 4.2.6 Example 1 97 4.2.7 Noise transformations at the output port 103 4.3 Equivalent InputNoise Power 104 4.3.1 Definition of the Equivalent Input Noise Power 104 4.3.2 Power Spectral Density 106 4.3.3 Correlation and Autocorrelation Function 107 4.3.4 Example 110 4.3.5 Summary 113 4.4 Noise Models for Electronic Circuit Components 114 4.4.1 General Characteristics of Electronic Circuit Noise 115 4.4.2 Resistor Noise Model 115 4.4.3 Diode Noise Model 117 4.4.4 Bipolar Transistor Noise Model 117 4.4.5 Field-Effect Transistor Noise Model 118 4.4.6 Example 120 4.4.7 Summary 123 4.5 Feedback network noise optimization 124 4.5.1 Generic Model for the Feedback Network 124 4.5.2 Magnification of Noise by the Feedback Network 125 4.5.3 Noise Production by the Feedback Network 127 4.5.4 Feedback Networks with Optimum Noise Performance 127 4.5.5 Impedance Feedback Networks 129 4.5.6 Example 134 4.6 Design of the nullor input stage 135 viii CONTENTS 4.7 Noise Optimizations 137 4.7.1 Noise matching to the source via a transformer 137 4.7.2 Optimization of the bias current 138 4.7.3 Connecting stages in-series/in-parallel 140 4.8 Exercises 142 5. NONLINEAR DISTORTION 151 5.1 Introduction 151 5.2 The origin of distortion 152 5.2.1 Clipping distortion 156 5.2.2 Weak distortion 158 5.3 Measures of distortion 166 5.3.1 Harmonic Distortion 167 5.3.2 Intercept points 168 5.3.3 Compression points 169 5.3.4 Intermodulation 169 5.4 Design for low distortion 170 5.4.1 Clippingdistortion 171 5.4.2 Weak distortion 174 5.5 Dynamic Nonlinear Distortion 176 5.5.1 Volterra Series 176 5.5.2 Behavior of CE stage 178 5.5.3 Behavior of Differential CE stage 181 5.6 Exercises 185 6. THE LOOP-GAIN-POLES PRODUCT 189 6.1 Introduction 189 6.2 The simple transistor model 190 6.3 The LP-product 191 6.4 Dominantpoles 193 6.5 Increasing the LP-product 195 6.5.1 Increasing the LP-product without increasing the order 195 6.5.2 Increasing the LP-product by increasing the order 197 6.6 The contribution to the LP-product of a (MOS)FET 199 6.7 What to do with a zero in the origin 199 6.8 Guaranteeing a negative loop gain 201 6.9 Exercises 203 ix 7. FREQUENCY COMPENSATION 207 7.1 Introduction 207 7.2 Model used for the frequency compensation 207 7.3 Model validation after frequency compensation 208 7.4 Frequency compensation via the root locus 211 7.4.1 Phantom zeros 213 7.4.2 Pole-splitting 220 7.4.3 Pole-zero cancellation 224 7.4.4 Resistive broad-banding 228 7.4.5 Changing the contribution to the LP-product 230 7.5 Conclusions 230 7.6 Exercises 231 8. BIASING 241 8.1 Introduction 241 8.2 General biasing rules and floating nodes 242 8.3 The ideal transactor and the real transistor 243 8.3.1 Biasing one transistor 244 8.3.2 Examples of control loops for a single transistor 246 8.3.3 The influence of the bias loops on the signal behavior 250 8.3.4 Biasing of differentialstages 251 8.4 Linear components 251 8.4.1 Resistors 252 8.4.2 Capacitors 254 8.4.3 Inductors 256 8.5 Biasing step 1: Identification and first implementation of the bias loops 256 8.6 Biasing step 2: The bias-current loops 257 8.6.1 Measuring DC-bias offset currents 257 8.6.2 Changing the topology of the current control loops 259 8.6.3 Floating nodes 261 8.7 Biasing step 3: The bias-voltage loops 263 8.7.1 Practical controlled DC-bias voltage sources 263 8.7.2 Capacitors as controlled voltage sources 264 8.7.3 Skipping the control of a bias voltage source 265 8.7.4 The voltage offsetcontrol at the input 266 8.8 Summary after biasing steps 2 and 3 268 8.9 Biasing step 4: Reduction of the number of bias sources 269