STRUCTURED COMPUTER ORGANIZATION SIXTH EDITION This page intentionally left blank STRUCTURED COMPUTER ORGANIZATION SIXTH EDITION ANDREW S. TANENBAUM Vrije Universiteit Amsterdam, The Netherlands TODD AUSTIN University of Michigan Ann Arbor, Michigan, United States Editorial Director, ECS: Marcia Horton Executive Editor: Tracy Johnson (Dunkelberger) Associate Editor: Carole Snyder Director of Marketing: Christy Lesko Marketing Manager: Yez Alayan Senior Marketing Coordinator: Kathryn Ferranti Director of Production: Erin Gregg Managing Editor: Jeff Holcomb Associate Managing Editor: Robert Engelhardt Manufacturing Buyer: Lisa McDowell Art Director: Anthony Gemmellaro Cover Illustrator: Jason Consalvo Manager, Rights and Permissions: Michael Joyce Media Editor: Daniel Sandin Media Project Manager: Renata Butera Printer/Binder: Courier/Westford Cover Printer: Lehigh-Phoenix Color/Hagerstown Credits and acknowledgments borrowed from other sources and reproduced, with permission, in this textbook appear in the Credits section in the end matter of this text. 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Library of Congress Cataloging-in-Publication Data Tanenbaum, Andrew S., Structured computer organization / Andrew S. Tanenbaum, Todd Austin. -- 6th ed. p. cm. Includes bibliographical references and index. ISBN-13: 978-0-13-291652-3 ISBN-10: 0-13-291652-5 1. Computer programming. 2. Computer organization. I. Austin, Todd. II. Title. QA76.6.T38 2013 005.1--dc23 2012021627 10 9 8 7 6 5 4 3 2 1 ISBN 10: 0-13-291652-5 ISBN 13: 978-0-13-291652-3 AST: Suzanne,Barbara,Marvin,AronandNathan TA: ToRoberta,whomadespace(andtime)formetofinishthisproject. This page intentionally left blank CONTENTS PREFACE xix 1 INTRODUCTION 1.1 STRUCTUREDCOMPUTERORGANIZATION 2 1.1.1 Languages,Levels,andVirtualMachines 2 1.1.2 ContemporaryMultilevelMachines 5 1.1.3 EvolutionofMultilevelMachines 8 1.2 MILESTONESINCOMPUTERARCHITECTURE 13 1.2.1 TheZerothGeneration—MechanicalComputers(1642–1945) 13 1.2.2 TheFirstGeneration—VacuumTubes(1945–1955) 16 1.2.3 TheSecondGeneration—Transistors(1955–1965) 19 1.2.4 TheThirdGeneration—IntegratedCircuits(1965–1980) 21 1.2.5 TheFourthGeneration—VeryLargeScaleIntegration(1980–?) 23 1.2.6 TheFifthGeneration—Low-PowerandInvisibleComputers 26 1.3 THECOMPUTERZOO 28 1.3.1 TechnologicalandEconomicForces 28 1.3.2 TheComputerSpectrum 30 1.3.3 DisposableComputers 31 1.3.4 Microcontrollers 33 1.3.5 MobileandGameComputers 35 1.3.6 PersonalComputers 36 1.3.7 Servers 36 1.3.8 Mainframes 38 vii viii CONTENTS 1.4 EXAMPLECOMPUTERFAMILIES 39 1.4.1 Introductiontothex86Architecture 39 1.4.2 IntroductiontotheARMArchitecture 45 1.4.3 IntroductiontotheAVRArchitecture 47 1.5 METRICUNITS 49 1.6 OUTLINEOFTHISBOOK 50 2 COMPUTER SYSTEMS 2.1 PROCESSORS 55 2.1.1 CPUOrganization 56 2.1.2 InstructionExecution 58 2.1.3 RISCversusCISC 62 2.1.4 DesignPrinciplesforModernComputers 63 2.1.5 Instruction-LevelParallelism 65 2.1.6 Processor-LevelParallelism 69 2.2 PRIMARYMEMORY 73 2.2.1 Bits 74 2.2.2 MemoryAddresses 74 2.2.3 ByteOrdering 76 2.2.4 Error-CorrectingCodes 78 2.2.5 CacheMemory 82 2.2.6 MemoryPackagingandTypes 85 2.3 SECONDARYMEMORY 86 2.3.1 MemoryHierarchies 86 2.3.2 MagneticDisks 87 2.3.3 IDEDisks 91 2.3.4 SCSIDisks 92 2.3.5 RAID 94 2.3.6 Solid-StateDisks 97 2.3.7 CD-ROMs 99 2.3.8 CD-Recordables 103 2.3.9 CD-Rewritables 105 2.3.10 DVD 106 2.3.11 Blu-ray 108 CONTENTS ix 2.4 INPUT/OUTPUT 108 2.4.1 Buses 108 2.4.2 Terminals 113 2.4.3 Mice 118 2.4.4 GameControllers 120 2.4.5 Printers 122 2.4.6 TelecommunicationsEquipment 127 2.4.7 DigitalCameras 135 2.4.8 CharacterCodes 137 2.5 SUMMARY 142 3 THE DIGITAL LOGIC LEVEL 3.1 GATESANDBOOLEANALGEBRA 147 3.1.1 Gates 148 3.1.2 BooleanAlgebra 150 3.1.3 ImplementationofBooleanFunctions 152 3.1.4 CircuitEquivalence 153 3.2 BASICDIGITALLOGICCIRCUITS 158 3.2.1 IntegratedCircuits 158 3.2.2 CombinationalCircuits 159 3.2.3 ArithmeticCircuits 163 3.2.4 Clocks 168 3.3 MEMORY 169 3.3.1 Latches 169 3.3.2 Flip-Flops 172 3.3.3 Registers 174 3.3.4 MemoryOrganization 174 3.3.5 MemoryChips 178 3.3.6 RAMsandROMs 180 3.4 CPUCHIPSANDBUSES 185 3.4.1 CPUChips 185 3.4.2 ComputerBuses 187 3.4.3 BusWidth 190 3.4.4 BusClocking 191 3.4.5 BusArbitration 196 3.4.6 BusOperations 198