ChCahpatpetre r130 Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Offs and Implementation Issues LucasCompassiSevero,AlessandroGirardi,AlessandroBofdeOliveira, FabioN.KeplerandMarciaC.Cera Additionalinformationisavailableattheendofthechapter http://dx.doi.org/10.5772//45872 1.Introduction The design of analog integrated circuits is complex because it involves several aspects of device modeling, computational methodologies, and human experience. Nowadays, the well-stablished CMOS (Complementary Metal-Oxide-Semiconductor) technology is mandatoryinmostoftheintegratedcircuits. ThebasicdevicesareMOStransistors, whose manufacturing process is well understood and constantly updated in the design of small devices. Detailed knowledge of the devices technology is needed for modeling all aspects of analog design, since there is a strong dependency between the circuit behavior and the manufacturingprocess. Contrarytodigitalcircuits,whicharecomposedbymillions(orevenbillions)oftransistors withequaldimensions, analogcircuitsareformedbytensoftransistors, buteachonewith a particular geometric feature and bias operation point. Digital design is characterized by the high degree of automation, in which the designer has low influence on the resulting physical circuit. The quality of the CAD (Computer-Aided Design) tools used for circuit synthesisismuchmoreimportantthanthedesignerexperience. Thesetoolsareabletodeal withalargenumberofdevicesandinterconnections. Digitalbinarycircuitshaverobustness characteristics in which the influence of non-linearities and non-idealities are not a major concern. Furthermore, mathematical models of devices for digital circuits are relaxed and computationallyveryefficient. Ontheotherhand,analogdesignstilllacksfromdesignautomation. Thisisaconsequence of the problem features and the difficulty of implementing generic tools with high design accuracy. Thus,thecomplexrelationsbetweendesignobjectivesanddesignvariablesresult in a highly non-linear n-dimensional system. Technology dependency limits the design automation, since electrical behavior is directly related to physical implementation. In ©2012Girardietal.,licenseeInTech.Thisisanopenaccesschapterdistributedunderthetermsofthe CreativeCommonsAttributionLicense(http://creativecommons.org/licenses/by/3.0),whichpermits unrestricteduse,distribution,andreproductioninanymedium,providedtheoriginalworkisproperly cited. 262 S2imulated Annealing – Single and Multiple Objective Problems Will-be-set-by-IN-TECH addition,thelargenumberofdifferentcircuittopologies,eachonewithuniquedetails,makes modelingaverydifficulttask. Ingeneral,thetraditionalanalogdesignflowisbasedontherepetitionofmanualoptimization and SPICE (Simulation Program with Integrated Circuit Emphasis) electrical simulations. For a given specification, a circuit topology is captured in a netlist containing devices and interconnections. Devices sizes, such as transistors width and length, or resistors and capacitorsvalues,arecalculatedmanually.TheverificationisperformedwiththeaidofSPICE modelsandtechnologyparametersinordertopredictthefinalperformanceinsilicon.Specific designgoalssuchasdissipatedpower,voltagegain,orphasemarginareachievedbymanual calculationandthenre-verifiedinsimulation. Oncethefinalperformanceismet,thedesign ispassedontoaphysicaldesignengineertocompletethelayout,performdesignrulechecks, andlayoutversusschematicverification. Thelayoutengineerpassestheextractedphysical designinformationbacktothecircuitdesignertorecheckthecircuitoperationontheelectrical level. Whenphysicaleffectscausethecircuittomissspecifications,severalmoreiterationsof thiscircuit-to-layoutloopmayberequired. Thisprocessisrepeatedforeachanalogblockin thecircuit,evenformakinganyrelativelysimplespecificationchange. Theamountoftime andhumanresourcesusedcanvary, dependingonthedesigncomplexityandthedesigner experience.However,evenforalargeandmostskilleddesignteam,theshorttime-to-market and strict design objectives are key issues of analog designs. Improvements in the analog designautomationcansavedesigntimeandeffort. In this chapter we analyze the Simulated Annealing (SA) meta-heuristic applied to adjust circuitparametersintransistorsizingautomationprocedureatelectricallevel.Previousworks have been done in the field of analog design automation to enable fast design at the block level.Differentstrategiesandapproacheshavebeenproposedduringtheevolutionofanalog designautomation,suchassimulation-basedoptimization[5,9,17],symbolicsimulation[10], artificialintelligence[6],manuallyderiveddesignequations[4,21],hierarchyandtopology selection [11], geometric programming [12, 16] and memetic algorithms [15]. The main difficulty encountered for wide spread usage of these tools is that they require appropriate modelingofbothdevices(technologydependent)andcircuittopologiesinordertoachieve thedesignobjectivesinareasonableprocessingtime. Moreover,theoptionofchoosingdifferentcircuittopologiesisalsodifficulttoimplementin adesignmethodologyortool, sincemostapproachesworkwithtopology-basedequations, limitingtheapplicationrange. Thepossibilityofaddingnewblocktopologiesmustalsobe included in the methodology, since it is critical to the design. The usage of optimization algorithms combined with design techniques seems to be a good solution when applied to specific applications. This is because a general solution most often proves to have short comings for fully exploiting the capabilities of the analog CMOS technology. The key requirementsofananalogsynthesistoolare:interactivitywiththeuser,flexibilityformultiple topologiesandreasonableresponsetime. Theinterfacewithanelectricalsimulatorandwith alayouteditorisalsoconvenient[8]. The remaining of this chapter is organized as follows. Section 2 explains the Simulated Annealing meta-heuristic, its parameters, and functions. Circuit modeling, as well as the parametersandfunctionsinvolved,aredescribedinSec.3.Afterward,Sec.4presentsabasic circuitusedtoexplaintheusageofSA,howthesearchesoccur,andtheresultsachieved. In Sec. 5, Simulated Annealing is used to seek solutions to a more complex circuit, in which wecouldanalyzetheimpactofSAparametersandfunctionsasameantoautomatecircuit design.Finally,Sec.6concludethischapterwithourfinalremarksandfutureworks. SimulatedSAimnneualliangtetodIm ApronvneAenaalloignIgnt etgora tIemdCpircruoitvDee sAignn:aTrlaodeg-O IfnfstaendgIrmaptleemden CtatiiorncuIssitu eDsesign: Trade-Off s and Implementation Issues3 263 2.Simulatedannealing The Simulated Annealing (SA) is a well known random-search technique that exploits an analogy with the way a metal heat and slowly freezes into a minimum energy crystalline structure, the so called annealing process. In a more general system, like an optimization problem, it is used for searching the minimum value of a cost function, avoiding getting trappedinlocalminima. Thealgorithmemploysrandomsearcheswhich,besidesaccepting solutionsthatdecrease(i.e. minimize)theobjectivecostfunction,mayalsoacceptsomethat increaseit.Thelatterarecalled“indirectsteps”,andareallowedinordertoescapefromlocal optima. ( ) TheSAalgorithmusesacoolingfunction T t ,whichmapsatimeinstantttoatemperature T, decreasing T astincreases. Ateachiteration, newstepsarerandomlytaken, basedona ( ) probabilisticstategenerationfunction g X ,leadingtonewstatesinthesolutionspace. Inthis contextXisavectorofdparameters,wheredisthedimensionalityofthesolutionspace. If astepleadstoastatewithaworsesolution,itisonlyeffectivelytaken,i.e. thenewstateis accepted,withaprobabilitylessthan1.Stateswithbettersolutionsarealwaysaccepted.This probabilityisgivenbyanacceptancefunctionh(ΔF): 1 h(ΔF)= (1) 1+exp(ΔF/T) Here,ΔF=Ft+1−Ftrepresentsthevariationofthecostfunctioncalculatedattwoconsecutive timesstepsFt+1andFt. The algorithm is able to reach an optimal solution on the choice of the cooling function and probabilisticstategenerationfunction. Ifthetemperatureincoolingfunctiondecreasestoofast, thesearchwillrunfaster,buttheSAalgorithmisnotguaranteedtofindtheglobaloptimum anymore[13]. Thismaybeacceptableifasolutionisneededinasmallamountoftimeand the solution space is well-know or presents high dimensionality. This is called Simulated Quenching (SQ) [1], and is useful when an approximate solution is sufficient. There are some common sets of options to choose from when implementing an SA algorithm. They aredescribedbelow. 2.1.Boltzmannannealing The Boltzmann annealing is the classical simulated annealing algorithm, using physics principles to choose the probabilistic state generation function in order to ensure convergence toaglobalminimum.ItemploysaGaussiandistributionforgeneratingnewstates: 1 (ΔX)2 ( )= (− ) g X exp (2) Boltz (2πT(t))d/2 2T(t) Here,ΔX=X−X anddisthenumberofdimensionalityofthesearchspace.TheBoltzman 0 coolingfunctionisdescribedas: T T (t)= 0 (3) Boltz log(t) whereT istheinitialtemperature,andtisthetimestep. 0 Geman and Geman in the classical paper [7] have proved that using Gaussian distribution togeneratenewstates(Eq.3)withtheBoltzmancoolingfunction(Eq.2)issufficienttoreach globalminimumofanoptimizationfunctionatinfinitetime. 264 S4imulated Annealing – Single and Multiple Objective Problems Will-be-set-by-IN-TECH 2.2.Fastannealing Fast Annealing is a variant of the Boltzmann Annealing [20] that uses as probabilistic state generationfunctiontheCauchydistribution: T ( )= g X (4) Fast (ΔX2+T(t))(d+1)/2 One advantage of the Cauchy distribution over the Gaussian distribution is its fatter tail. Whenthetemperaturedecreases,theCauchydistributiongeneratesnewstateswithalower dispersionthanstatesgeneratedbyaGaussiandistribution. Inthiswaytheconvergeusing Cauchydistributionbecomesfaster. However, in order to guarantee that the algorithm reaches the global minimum, a special coolingfunctionisused: T T (t)= 0 (5) Fast t Where T is the initial temperature, and t is the time step. It is important to show that the 0 cooling function used in Boltzmann Annealing (equation 3) decreases more slowly than the coolingfunctionusedinFastAnnealing(equation5).Thischaracteristicturnstheconvergence ofFastannealingfasterthanBoltzmannannealing. 2.3.Reannealing Thereannealingmethod[14]raisesthetemperatureperiodicallyafterthealgorithmacceptsa certainnumberofnewstatesorafteragivennumberofiterations.Thenthesearchisrestarted withanewannealingtemperature.Thereannealingobjectiveistoavoidlocalminima,which presentsinterestingresultswhenappliedinnonlinearoptimizationproblems. 2.4.SimulatedQuenching SimulatedQuenching(SQ)[1],describedbefore,isusefulwhenanapproximatedsolutionis sufficientandthereisaneedoffasterexecutiontime. Anexampleofthefunctionthatcanbe usedtodecreasethetemperaturefasteristheexponentialcoolingfunctionshownbelow. T (t)=T ·0.95t (6) Exp 0 Using this cooling function with Boltzmann state generation function (Eq. 2) or Fast state generationfunction(Eq.4)willturntheoptimizationfaster,butwithoutconvergenceguarantee. 3.Circuitmodeling InordertodesignananalogintegratedcircuitwithSimulatedAnnealingoptimizationsitis necessary to develop a cost function describing the analog circuit behavior. There are two ways to analyze a circuit behavior. One is based on simplified equations as cost functions, which represent the circuit. This is the faster alternative, but has low precision and limits thesolutionsinsomeregionsofcircuitoperation. TheotherwayistouseanexternalSPICE electricalsimulatortoevaluatethecircuitwithacompletemodel. Thisalternativeprovides betteraccuracy,butdemandsmorecomputationalpower. SimulatedSAimnneualliangtetodIm ApronvneAenaalloignIgnt etgora tIemdCpircruoitvDee sAignn:aTrlaodeg-O IfnfstaendgIrmaptleemden CtatiiorncuIssitu eDsesign: Trade-Off s and Implementation Issues5 265 In this work the second alternative is used, with the electrical simulation performed by Synopsys HSpice ®. In the optimization procedure of analog integrated circuit design, the heuristic parameters are the MOSFET transistor sizes W (channel width) and L (channel length),voltageandcurrentsourcesbias,andcapacitorsandresistorvalues.Thedesignflow usingSimulatedAnnealingproposedinthischapterisshowninFigure1. Theproposedmethodologyhasthreespecificationstructuresasinputs: • Designconstraintsthatrepresentallfunctionsofcircuitspecificationsandvariablebounds; • AtechnologyfilecontainingsimulationmodelparametersfortheMOSFETtransistors;and • SA Options for the configuration of the SA heuristic, such as temperature function, annealingfunctionandstopcondition. The methodology starts with the initial solution generation that is provided by random generatednumbersaccordingtothevariablesboundsvalues.Thecircuitspecificationsofthe generatedsolutionarethenevaluatedbythecostfunction,whichusestheexternalelectrical SPICE simulator. Thereafter, the SA temperature parameter is initialized with the value specifiedintheSAoptions. Thereafter, a new solution is generated by the SA state generation function (see Section 2), and evaluated by the cost function by means of electrical simulations. The new solution is comparedwiththecurrentsolutionand,ifithasalowercostfunctionvalue,itreplacesthe currentsolution.Otherwise,arandomnumberisgeneratedandcomparedwithaprobability parameter: ifitisgreater,thecurrentsolutionisreplacedbythenewsolution;ifsmaller,the newsolutionisrejected. Finally,thestoppingconditionsareverifiedand,ifsatisfied,theoptimizationprocessends.If notsatisfied,thetemperatureparameterisreducedbythecoolingfunctionandtheprocedure continues. The stopping conditions usually include a minimum value of temperature, a minimumcostfunctionvariation,andamaximumnumberofiterations. For analog design automation, a multi-objective cost function is necessary to aggregate different - and sometimes conflicting - circuit specifications. A typical multi-objective cost functioncanbe: n m ( )= ∑ ( )+∑ ( ) fc X Si X Rj X (7) i=1 j=1 In this function, the first sum represents optimization specifications (design objectives) and thesecondonethedesignconstraints. S(X)istheith circuitspecificationvalueand R (X)) i j isthejthconstraintfunction. BotharefunctionsofthevectorXofdesignparametersandare normalizedandtunedaccordingtothedesiredcircuitperformance. ( ) R X is a function that is dependent on the specification type: minimum required value j ( ) ( ) (Rmin X ) or maximum required value (Rmax X ) [3]. These functions are shown in Fig. 2, where a is the maximum or minimum required value and b is the bound value between acceptableandunacceptableperformancevalues. Acceptablebutnon-feasibleperformance valuesarethatpointsbetween a and b. Theyreturnintermediatevaluesfortheconstraints functionsinordertoallowtheexplorationofdisconnectfeasibledesignspaceregions. These functionsreturnadditionalcostforthecostfunctioniftheperformanceisoutsidethedesired range.Otherwise,theadditionalcostiszero. 266 S6imulated Annealing – Single and Multiple Objective Problems Will-be-set-by-IN-TECH Random Design InitialSolution Constraints Generation Simulated Anneling core Technology Initialize File Temperature NestSolution CostFunction SAOptions Generation Evaluation Temperature Acceptance Electrical Reduction Testing Simulation Stop No condition satisfied? Yes End: Circuit Designed Figure1.AnalogintegratedcircuitsizingwithSimulatedAnnealingflow. 4.Basicanalysisofthesearchspace Thissectionpresentsasimplecasestudy,adifferentialamplifier,tointroduceandexplainthe usageofSimulatedAnnealingtoautomatethedesignofanalogintegratedcircuit.Section4.1 describes the features of the differential amplifier. Sec. 4.2 explains the modeling of the differentialamplifierthatallowsitssimulationandtheusageoftheSA.Finally, toimprove the automation process, some optimization options on SA are applied and their results are discussedinSec.4.3. 4.1.Casestudy: Differentialamplifier A differential amplifier is a basic analog building block used in general as the input stage of operational amplifiers. Perhaps its simplicity, it is very useful as a first voltage SimulatedSAimnneualliangtetodIm ApronvneAenaalloignIgnt etgora tIemdCpircruoitvDee sAignn:aTrlaodeg-O IfnfstaendgIrmaptleemden CtatiiorncuIssitu eDsesign: Trade-Off s and Implementation Issues7 267 f(S) f(S) j j f f MAX MAX Feasible Feasible b a a b Unacceptable Acceptable Acceptable Unacceptable (a) (b) Figure2.Costfunctionperformancemetrics:(a)minimumrequiredvaluespecificationsand(b) maximumrequiredvaluespecifications. amplificationstageofmanyelectronicdevicesandhasbecomethedominantchoiceintoday’s high-performance analog and mixed-signal circuits [19]. Ideally, it amplifies the difference betweentwovoltagesbutdoesnotamplifythecommon-modevoltages. Animplementation of the differential amplifier with CMOS transistors and active load is shown in Fig. 3 . It is composed by a differential pair formed by two input transistors (M1 and M2), an active current mirror (M3 and M4) and an ideal tail current source Iref. The output voltage Vout depends on the difference between the input voltages V and V . For a small difference in1 in2 betweenV andV ,both M2and M4aresaturated,providingahighgain. Otherwise,if in1 in2 | − | V V islargeenough, M1or M2willbeoffandtheoutputwillbestuckat0V orat in1 in2 V . DD The output voltage of the differential amplifier can be expressed in terms of its differential-modeandcommon-modeinputvoltagesas (cid:2) (cid:3) + V V Vout = AVD(Vin1−Vin2)±AVC in1 2 in2 (8) where A is the differential-mode voltage gain and A is the common-mode voltage VD VC gain. Anidealoperationalamplifierhasaninfinite A andzero A . Althoughpractical VD VC implementationstrytofindanapproximationtothesevalues,theimplementationofphysical circuitsinsertsomenon-idealitiesthatlimitA andA . VD VC Anotherimportantcharacteristicofadifferentialamplifieristheinputcommon-moderange = (ICMR).WecanestimateICMRbysettingV V andvaryinputcommon-modevoltage in1 in2 (DCcomponentofV andV )untiloneofthetransistorsinthecircuitisnolongersaturated in1 in2 + [2].Thehighestcommon-modeinputvoltage(ICMR )is + = − + ICMR V V V (9) DD SG3 TN1 Here,V isthesource-voltageoftransistorM3andV isthethresholdvoltageofM1.The SG3 TN1 lowestinputvoltageatthegateofM1(orM2)isfoundtobe − = + + ICMR V V V (10) SS 1 GS2 Thevoltageatnode1(V )isdeterminedbythephysicalimplementationofthecurrentsource 1 I ,whichingeneralisasingletransistorwhosedraincurrentiscontrolledbyitsgatevoltage. ref V isthegate-sourcevoltageoftransistorM2. GS2 268 S8imulated Annealing – Single and Multiple Objective Problems Will-be-set-by-IN-TECH The small-signal properties of the differential amplifier can be accomplished with the assistanceofthesimplifiedmodelshowninFig.4,whichignoresbodyeffect. Inthisfigure, gm is the gate transconductance given by the derivative of the drain current in relation to gate-sourcevoltage: ∂I gm= D (11) ∂V GS Theseriesresistancerdsistheinverseoftheoutputconductancegdsandcanbeestimatedin small-signalanalysisas 1 ∂I =gds= D (12) rds ∂V DS V DD M3 M4 2 3 Vout Vin1 M1 M2 Vin2 1 I ref V SS Figure3.SchematicsofaCMOSdifferentialamplifier. C3 G++1vin1−vin2−G+2 D1=G3=D3=G4 vgs1 vgs2 gm1·vgs1 rds1 rds3 1/gm3 C1 I3 rds2 rds4 C2 Vout − − gm1·vgs1 S1=S2=S3=S4 Figure4.Simplifiedsmall-signalmodelfortheCMOSdifferentialamplifier. Thesmall-signalvoltagegainAvo,i.e.,therelationshipbetweenVoutandthedifferentialinput − voltageV V ,canbeestimatedinlowfrequenciesby in1 in2 gm Avo = +1 (13) gds gds 2 4 Forhigherfrequencies,thevoltagegainismodifiedduetothevariousparasiticcapacitorsat eachnodeofthecircuits,modeledbyC ,C andC ,whicharecalculatedasfollows: 1 2 3 SimulatedSAimnneualliangtetodIm ApronvneAenaalloignIgnt etgora tIemdCpircruoitvDee sAignn:aTrlaodeg-O IfnfstaendgIrmaptleemden CtatiiorncuIssitu eDsesign: Trade-Off s and Implementation Issues9 269 = + + + + C C C C C C (14) 1 gd1 bd1 bd3 gs3 gs4 = + + + C C C C C (15) 2 bd2 bd4 gd2 L = C C (16) 3 gd4 ConsideringC approximatelyzero,thevoltage-transferfunctioncanbewrittenas 3 (cid:4)(cid:2) (cid:3) (cid:5) Vout(s)∼= gdsg+m1gds gmgm+3sC Vgs1(s)−Vgs2(s) s+ω2ω (17) 2 4 3 1 2 whereω isgivenas 2 + gds gds ω = 2 4 (18) 2 C 2 The pole ω2 determines the cut-off frequency of the amplifier and is also called as ω−3dB. Assumingthat + gm gds gds 3 (cid:3) 2 4 (19) C C 1 2 thenthefrequencyresponseofthedifferentialamplifierreducesto (cid:2) (cid:3)(cid:2) (cid:3) Vout(s) ∼= gm1 ω2 (20) V (s)−V (s) gds +gds s+ω in1 in2 2 4 2 −( + ) This first-order analysis leads to a single pole at the output given by gds gds /C . 2 4 2 Some zeroes occur due to C , C and C , but they can be ignored in this analysis. gd1 gd2 gd4 Thegain-bandwidthproduct(GBW),whichistheequaltotheunity-gainfrequency, canbe expressedas GBW = Avo·ω−3dB (21) Theslew-rate(SR)performanceoftheCMOSdifferentialamplifierdependsthevalueof I ref andthecapacitancefromtheoutputnodetoacgroundandisgivenby I = ref SR (22) C where C is the total capacitance connected to the output node (approximated by C in our 2 analysis). Otherimportantspecificationsfortheelectricalbehaviorofthedifferentialamplifierincludes = ·( − ) powerdissipationP I V V andtotalgatearea,calculatedasthesumofthe diss ref DD SS productofgatewidthandlenghtofalltransistorsthatcomposethecircuit: =∑ · Area W L (23) i i i All analog design has a target fabrication technology and a device type, in which the set of transistor model parameters is unique. These parameters determines the electrical characteristics-suchasdraincurrent,gatetransconductanceandoutputconductance-ofthe activedevicesthatarepartofthecircuit. Thespecificationsdescribedbeforearefunctionof theseparameters,togetherwithWandL.Sincetheparametersarefixedforagivenfabrication 270 S10imulated Annealing – Single and Multiple Objective Problems Will-be-set-by-IN-TECH technology,thedesignerhasasfreevariablesonlythegatesizes. Gatesizingis,ineffect,the taskofanalogdesign. 4.2.Modelingthedifferentialamplifierforautomaticsynthesis ThemodelingofthedifferentialamplifierofFig.3forautomaticsynthesisisstraightforward. Using a simulation-based approach, the circuit specifications are calculated by SPICE electrical simulations. As an example, let us consider the multi-objective design of a differential amplifier that must be optimized in terms of voltage gain Avo and positive + input common-mode range ICMR . Also, there is a list of constraints containing a series of specifications that must be met hardly. Table 1 summarizes the design objectives and constraintsforthisproblem. Specification Value Av maximize + ICMR maximize Area <120μm2 ◦ PM >70 GBW >100MHz Table1.DesignspecificationsandconstraintsforthedifferentialamplifierofFig3. ( ) Thecostfunction fc X isthanformulatedasasumofdesignspecificationsandconstraints intermsofthevectorofthedesignvariablesX: +( ) ( ) ( )= · ICMR X + Avo X + ( ) fc X 3 + R X (24) ICMRref Avo(ref) Thespecificationsarecalculatedforagiven X andnormalizedbyareferencevalue. Inthis + = = example, ICMRref 1.3V and Avo(ref) 20dB. The ponderation of each specification can be implemented with individual weights which indicate the relative importance of the + ( ) parameter. In this example, we choose a weight of 3 for ICMR and 1 for Avo. R X is a constraintfunctionwhichisalsoafunctionofX,calculatedasfollows: ( ( ) ) ( )= Rmax Area X ,Arearef + ( ( ) )+ ( ( ) ) R X 4 Rmin PM X ,PMref Rmax GBW X ,GBWref (25) ( ( ) ) ( ( ) ) Here, Rmax S X ,Sref and Rmin S X ,Sref are constraint functions of maximum and ( ) minimum, respectively, intermsofthespecification S X andthereferencevalue S . For ref ( ( ) ) example, the constraint of gate area is related to Rmax S X ,Sref , because it can not be largerthanareferencevalueof Area . ThesameoccursforGBW,whichcannotbesmaller ref ( ( ) ) thanGBW ,whoseconstraintismodeledbythefunctionR S X ,S . Bothconstraint ref min ref ( ) functions insert a penalty value in the cost function fc X if the specification is outside the expected range. Otherwise, they return zero. The following equations show how the constraintfunctionsareimplemented: (cid:6) ( )≤ 0 ifS X S Rmax(S(X),Sref)= S(X)−Sref ifS(X)>Sref (26) Sref ref