We are IntechOpen, the world’s leading publisher of Open Access books Built by scientists, for scientists 6,200 169,000 185M Open access books available International authors and editors Downloads Our authors are among the 154 TOP 1% 12.2% Countries delivered to most cited scientists Contributors from top 500 universities Selection of our books indexed in the Book Citation Index in Web of Science™ Core Collection (BKCI) Interested in publishing with us? Contact [email protected] Numbers displayed above are based on latest data collected. For more information visit www.intechopen.com ChCahpatpetre r130 Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Offs and Implementation Issues LucasCompassiSevero,AlessandroGirardi,AlessandroBofdeOliveira, FabioN.KeplerandMarciaC.Cera Additionalinformationisavailableattheendofthechapter http://dx.doi.org/10.5772//45872 1. Introduction The design of analog integrated circuits is complex because it involves several aspects of device modeling, computational methodologies, and human experience. Nowadays, the well-stablished CMOS (Complementary Metal-Oxide-Semiconductor) technology is mandatory in most of the integrated circuits. The basic devices are MOS transistors, whose manufacturing process is well understood and constantly updated in the design of small devices. Detailed knowledge of the devices technology is needed for modeling all aspects of analog design, since there is a strong dependency between the circuit behavior and the manufacturingprocess. Contrary to digital circuits, which are composed by millions (or even billions) of transistors with equal dimensions, analog circuits are formed by tens of transistors, but each one with a particular geometric feature and bias operation point. Digital design is characterized by the high degree of automation, in which the designer has low influence on the resulting physical circuit. The quality of the CAD (Computer-Aided Design) tools used for circuit synthesis is much more important than the designer experience. These tools are able to deal with a large number of devices and interconnections. Digital binary circuits have robustness characteristics in which the influence of non-linearities and non-idealities are not a major concern. Furthermore, mathematical models of devices for digital circuits are relaxed and computationallyveryefficient. On the other hand, analog design still lacks from design automation. This is a consequence of the problem features and the difficulty of implementing generic tools with high design accuracy. Thus, the complex relations between design objectives and design variables result in a highly non-linear n-dimensional system. Technology dependency limits the design automation, since electrical behavior is directly related to physical implementation. In ©2012Girardietal.,licenseeInTech.Thisisanopenaccesschapterdistributedunderthetermsofthe CreativeCommonsAttributionLicense(http://creativecommons.org/licenses/by/3.0),whichpermits unrestricteduse,distribution,andreproductioninanymedium,providedtheoriginalworkisproperly cited. 262 Simulated Annealing – Single and Multiple Objective Problems 2 Will-be-set-by-IN-TECH addition,thelargenumberofdifferentcircuittopologies,eachonewithuniquedetails,makes modelingaverydifficulttask. Ingeneral,thetraditionalanalogdesignflowisbasedontherepetitionofmanualoptimization and SPICE (Simulation Program with Integrated Circuit Emphasis) electrical simulations. For a given specification, a circuit topology is captured in a netlist containing devices and interconnections. Devices sizes, such as transistors width and length, or resistors and capacitorsvalues,arecalculatedmanually. TheverificationisperformedwiththeaidofSPICE modelsandtechnologyparametersinordertopredictthefinalperformanceinsilicon. Specific designgoalssuchasdissipatedpower,voltagegain,orphasemarginareachievedbymanual calculation and then re-verified in simulation. Once the final performance is met, the design ispassedontoaphysicaldesignengineertocompletethelayout,performdesignrulechecks, and layout versus schematic verification. The layout engineer passes the extracted physical designinformationbacktothecircuitdesignertorecheckthecircuitoperationontheelectrical level. Whenphysicaleffectscausethecircuittomissspecifications,severalmoreiterationsof this circuit-to-layout loop may be required. This process is repeated for each analog block in the circuit, even for making any relatively simple specification change. The amount of time and human resources used can vary, depending on the design complexity and the designer experience. However,evenforalargeandmostskilleddesignteam,theshorttime-to-market and strict design objectives are key issues of analog designs. Improvements in the analog designautomationcansavedesigntimeandeffort. In this chapter we analyze the Simulated Annealing (SA) meta-heuristic applied to adjust circuitparametersintransistorsizingautomationprocedureatelectricallevel. Previousworks have been done in the field of analog design automation to enable fast design at the block level. Differentstrategiesandapproacheshavebeenproposedduringtheevolutionofanalog designautomation,suchassimulation-basedoptimization[5,9,17],symbolicsimulation[10], artificial intelligence [6], manually derived design equations [4, 21], hierarchy and topology selection [11], geometric programming [12, 16] and memetic algorithms [15]. The main difficulty encountered for wide spread usage of these tools is that they require appropriate modeling of both devices (technology dependent) and circuit topologies in order to achieve thedesignobjectivesinareasonableprocessingtime. Moreover, the option of choosing different circuit topologies is also difficult to implement in a design methodology or tool, since most approaches work with topology-based equations, limiting the application range. The possibility of adding new block topologies must also be included in the methodology, since it is critical to the design. The usage of optimization algorithms combined with design techniques seems to be a good solution when applied to specific applications. This is because a general solution most often proves to have short comings for fully exploiting the capabilities of the analog CMOS technology. The key requirementsofananalogsynthesistoolare: interactivitywiththeuser,flexibilityformultiple topologies and reasonable response time. The interface with an electrical simulator and with alayouteditorisalsoconvenient[8]. The remaining of this chapter is organized as follows. Section 2 explains the Simulated Annealing meta-heuristic, its parameters, and functions. Circuit modeling, as well as the parametersandfunctionsinvolved,aredescribedinSec.3. Afterward,Sec.4presentsabasic circuit used to explain the usage of SA, how the searches occur, and the results achieved. In Sec. 5, Simulated Annealing is used to seek solutions to a more complex circuit, in which we could analyze the impact of SA parameters and functions as a mean to automate circuit design. Finally,Sec.6concludethischapterwithourfinalremarksandfutureworks. Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Off s and Implementation Issues 263 SimulatedAnnealingtoImproveAnalogIntegratedCircuitDesign:Trade-OffsandImplementationIssues 3 2. Simulated annealing The Simulated Annealing (SA) is a well known random-search technique that exploits an analogy with the way a metal heat and slowly freezes into a minimum energy crystalline structure, the so called annealing process. In a more general system, like an optimization problem, it is used for searching the minimum value of a cost function, avoiding getting trapped in local minima. The algorithm employs random searches which, besides accepting solutions that decrease (i.e. minimize) the objective cost function, may also accept some that increaseit. Thelatterarecalled“indirectsteps”,andareallowedinordertoescapefromlocal optima. The SA algorithm uses a cooling function T(t), which maps a time instant t to a temperature T, decreasing T as t increases. At each iteration, new steps are randomly taken, based on a probabilistic state generation function g(X), leading to new states in the solution space. In this context X is a vector of d parameters, where d is the dimensionality of the solution space. If a step leads to a state with a worse solution, it is only effectively taken, i.e. the new state is accepted,withaprobabilitylessthan1. Stateswithbettersolutionsarealwaysaccepted. This probabilityisgivenbyanacceptancefunction h(ΔF): 1 h(ΔF) = (1) 1+exp(ΔF/T) Here,ΔF = F −F representsthevariationofthecostfunctioncalculatedattwoconsecutive t+1 t timessteps F and F. t+1 t The algorithm is able to reach an optimal solution on the choice of the cooling function and probabilistic state generation function. If the temperature in cooling function decreases too fast, the search will run faster, but the SA algorithm is not guaranteed to find the global optimum anymore [13]. This may be acceptable if a solution is needed in a small amount of time and the solution space is well-know or presents high dimensionality. This is called Simulated Quenching (SQ) [1], and is useful when an approximate solution is sufficient. There are some common sets of options to choose from when implementing an SA algorithm. They aredescribedbelow. 2.1. Boltzmann annealing The Boltzmann annealing is the classical simulated annealing algorithm, using physics principles to choose the probabilistic state generation function in order to ensure convergence toaglobalminimum. ItemploysaGaussiandistributionforgeneratingnewstates: 1 (ΔX)2 g (X) = exp(− ) (2) Boltz (2πT(t))d/2 2T(t) Here,ΔX = X−X anddisthenumberofdimensionalityofthesearchspace. TheBoltzman 0 coolingfunctionisdescribedas: T 0 T (t) = (3) Boltz log(t) where T istheinitialtemperature,andtisthetimestep. 0 Geman and Geman in the classical paper [7] have proved that using Gaussian distribution to generate new states (Eq. 3) with the Boltzman cooling function (Eq. 2) is sufficient to reach globalminimumofanoptimizationfunctionatinfinitetime. 264 Simulated Annealing – Single and Multiple Objective Problems 4 Will-be-set-by-IN-TECH 2.2. Fast annealing Fast Annealing is a variant of the Boltzmann Annealing [20] that uses as probabilistic state generationfunctiontheCauchydistribution: T g (X) = (4) Fast (ΔX2+T(t))(d+1)/2 One advantage of the Cauchy distribution over the Gaussian distribution is its fatter tail. When the temperature decreases, the Cauchy distribution generates new states with a lower dispersion than states generated by a Gaussian distribution. In this way the converge using Cauchydistributionbecomesfaster. However, in order to guarantee that the algorithm reaches the global minimum, a special coolingfunctionisused: T 0 T (t) = (5) Fast t Where T is the initial temperature, and t is the time step. It is important to show that the 0 cooling function used in Boltzmann Annealing (equation 3) decreases more slowly than the coolingfunctionusedinFastAnnealing(equation5). Thischaracteristicturnstheconvergence ofFastannealingfasterthanBoltzmannannealing. 2.3. Reannealing Thereannealingmethod[14]raisesthetemperatureperiodicallyafterthealgorithmacceptsa certainnumberofnewstatesorafteragivennumberofiterations. Thenthesearchisrestarted withanewannealingtemperature. Thereannealingobjectiveistoavoidlocalminima,which presentsinterestingresultswhenappliedinnonlinearoptimizationproblems. 2.4. Simulated Quenching Simulated Quenching (SQ) [1], described before, is useful when an approximated solution is sufficientandthereisaneedoffasterexecutiontime. Anexampleofthefunctionthatcanbe usedtodecreasethetemperaturefasteristheexponentialcoolingfunctionshownbelow. T (t) = T ·0.95t (6) Exp 0 Using this cooling function with Boltzmann state generation function (Eq. 2) or Fast state generationfunction(Eq.4)willturntheoptimizationfaster,butwithoutconvergenceguarantee. 3. Circuit modeling In order to design an analog integrated circuit with Simulated Annealing optimizations it is necessary to develop a cost function describing the analog circuit behavior. There are two ways to analyze a circuit behavior. One is based on simplified equations as cost functions, which represent the circuit. This is the faster alternative, but has low precision and limits the solutions in some regions of circuit operation. The other way is to use an external SPICE electrical simulator to evaluate the circuit with a complete model. This alternative provides betteraccuracy,butdemandsmorecomputationalpower. Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Off s and Implementation Issues 265 SimulatedAnnealingtoImproveAnalogIntegratedCircuitDesign:Trade-OffsandImplementationIssues 5 In this work the second alternative is used, with the electrical simulation performed by Synopsys HSpice ®. In the optimization procedure of analog integrated circuit design, the heuristic parameters are the MOSFET transistor sizes W (channel width) and L (channel length),voltageandcurrentsourcesbias,andcapacitorsandresistorvalues. Thedesignflow usingSimulatedAnnealingproposedinthischapterisshowninFigure1. Theproposedmethodologyhasthreespecificationstructuresasinputs: • Designconstraintsthatrepresentallfunctionsofcircuitspecificationsandvariablebounds; • AtechnologyfilecontainingsimulationmodelparametersfortheMOSFETtransistors;and • SA Options for the configuration of the SA heuristic, such as temperature function, annealingfunctionandstopcondition. The methodology starts with the initial solution generation that is provided by random generatednumbersaccordingtothevariablesboundsvalues. Thecircuitspecificationsofthe generated solution are then evaluated by the cost function, which uses the external electrical SPICE simulator. Thereafter, the SA temperature parameter is initialized with the value specifiedintheSAoptions. Thereafter, a new solution is generated by the SA state generation function (see Section 2), and evaluated by the cost function by means of electrical simulations. The new solution is compared with the current solution and, if it has a lower cost function value, it replaces the currentsolution. Otherwise,arandomnumberisgeneratedandcomparedwithaprobability parameter: if it is greater, the current solution is replaced by the new solution; if smaller, the newsolutionisrejected. Finally,thestoppingconditionsareverifiedand,ifsatisfied,theoptimizationprocessends. If notsatisfied,thetemperatureparameterisreducedbythecoolingfunctionandtheprocedure continues. The stopping conditions usually include a minimum value of temperature, a minimumcostfunctionvariation,andamaximumnumberofiterations. For analog design automation, a multi-objective cost function is necessary to aggregate different - and sometimes conflicting - circuit specifications. A typical multi-objective cost functioncanbe: n m f (X) = ∑ S (X)+ ∑ R (X) (7) c i j i=1 j=1 In this function, the first sum represents optimization specifications (design objectives) and the second one the design constraints. S (X) is the ith circuit specification value and R (X)) i j is the jth constraint function. Both are functions of the vector X of design parameters and are normalizedandtunedaccordingtothedesiredcircuitperformance. R (X) is a function that is dependent on the specification type: minimum required value j (R (X)) or maximum required value (R (X)) [3]. These functions are shown in Fig. 2, min max where a is the maximum or minimum required value and b is the bound value between acceptable and unacceptable performance values. Acceptable but non-feasible performance values are that points between a and b. They return intermediate values for the constraints functionsinordertoallowtheexplorationofdisconnectfeasibledesignspaceregions. These functionsreturnadditionalcostforthecostfunctioniftheperformanceisoutsidethedesired range. Otherwise,theadditionalcostiszero. 266 Simulated Annealing – Single and Multiple Objective Problems 6 Will-be-set-by-IN-TECH Random Design Initial Solution Constraints Generation Simulated Anneling core Technology Initialize File Temperature Nest Solution Cost Function SA Options Generation Evaluation Temperature Acceptance Electrical Reduction Testing Simulation Stop No condition satisfied? Yes End: Circuit Designed Figure1. AnalogintegratedcircuitsizingwithSimulatedAnnealingflow. 4. Basic analysis of the search space Thissectionpresentsasimplecasestudy,adifferentialamplifier,tointroduceandexplainthe usageofSimulatedAnnealingtoautomatethedesignofanalogintegratedcircuit. Section4.1 describes the features of the differential amplifier. Sec. 4.2 explains the modeling of the differential amplifier that allows its simulation and the usage of the SA. Finally, to improve the automation process, some optimization options on SA are applied and their results are discussedinSec.4.3. 4.1. Case study: Differential amplifier A differential amplifier is a basic analog building block used in general as the input stage of operational amplifiers. Perhaps its simplicity, it is very useful as a first voltage Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Off s and Implementation Issues 267 SimulatedAnnealingtoImproveAnalogIntegratedCircuitDesign:Trade-OffsandImplementationIssues 7 f(S) f(S) j j f f MAX MAX Feasible Feasible b a a b Unacceptable Acceptable Acceptable Unacceptable (a) (b) Figure2. Costfunctionperformancemetrics: (a)minimumrequiredvaluespecificationsand(b) maximumrequiredvaluespecifications. amplificationstageofmanyelectronicdevicesandhasbecomethedominantchoiceintoday’s high-performance analog and mixed-signal circuits [19]. Ideally, it amplifies the difference between two voltages but does not amplify the common-mode voltages. An implementation of the differential amplifier with CMOS transistors and active load is shown in Fig. 3 . It is composed by a differential pair formed by two input transistors (M1 and M2), an active current mirror (M3 and M4) and an ideal tail current source I . The output voltage V ref out depends on the difference between the input voltages V and V . For a small difference in1 in2 between V and V , both M2 and M4 are saturated, providing a high gain. Otherwise, if in1 in2 |V −V | is large enough, M1 or M2 will be off and the output will be stuck at 0V or at in1 in2 V . DD The output voltage of the differential amplifier can be expressed in terms of its differential-modeandcommon-modeinputvoltagesas V +V V = A (V −V )± A in1 in2 (8) out VD in1 in2 VC 2 (cid:2) (cid:3) where A is the differential-mode voltage gain and A is the common-mode voltage VD VC gain. An ideal operational amplifier has an infinite A and zero A . Although practical VD VC implementationstrytofindanapproximationtothesevalues,theimplementationofphysical circuitsinsertsomenon-idealitiesthatlimit A and A . VD VC Another important characteristic of a differential amplifier is the input common-mode range (ICMR). WecanestimateICMRbysettingV = V andvaryinputcommon-modevoltage in1 in2 (DCcomponentofV andV )untiloneofthetransistorsinthecircuitisnolongersaturated in1 in2 [2]. Thehighestcommon-modeinputvoltage(ICMR+)is ICMR+ = V −V +V (9) DD SG3 TN1 Here,V isthesource-voltageoftransistor M3andV isthethresholdvoltageof M1. The SG3 TN1 lowestinputvoltageatthegateof M1(or M2)isfoundtobe ICMR− = V +V +V (10) SS 1 GS2 Thevoltageatnode1(V )isdeterminedbythephysicalimplementationofthecurrentsource 1 I ,whichingeneralisasingletransistorwhosedraincurrentiscontrolledbyitsgatevoltage. ref V isthegate-sourcevoltageoftransistor M2. GS2 268 Simulated Annealing – Single and Multiple Objective Problems 8 Will-be-set-by-IN-TECH The small-signal properties of the differential amplifier can be accomplished with the assistance of the simplified model shown in Fig. 4, which ignores body effect. In this figure, gm is the gate transconductance given by the derivative of the drain current in relation to gate-sourcevoltage: ∂I D gm = (11) ∂V GS Theseriesresistance rds istheinverseoftheoutputconductance gds andcanbeestimatedin small-signalanalysisas 1 ∂I D = gds = (12) rds ∂V DS V DD M3 M4 2 3 Vout Vin1 M1 M2 Vin2 1 I ref V SS Figure3. SchematicsofaCMOSdifferentialamplifier. C3 G++1vin1−vin2−G+2 D1=G3=D3=G4 vgs1 vgs2 gm1·vgs1 rds1 rds3 1/gm3 C1 I3 rds2 rds4 C2 Vout − − gm1·vgs1 S1=S2=S3=S4 Figure4. Simplifiedsmall-signalmodelfortheCMOSdifferentialamplifier. Thesmall-signalvoltagegain A ,i.e.,therelationshipbetweenV andthedifferentialinput vo out voltageV −V ,canbeestimatedinlowfrequenciesby in1 in2 gm A = 1 (13) vo gds +gds 2 4 For higher frequencies, the voltage gain is modified due to the various parasitic capacitors at eachnodeofthecircuits,modeledbyC ,C andC ,whicharecalculatedasfollows: 1 2 3 Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Off s and Implementation Issues 269 SimulatedAnnealingtoImproveAnalogIntegratedCircuitDesign:Trade-OffsandImplementationIssues 9 C = C +C +C +C +C (14) 1 gd1 bd1 bd3 gs3 gs4 C = C +C +C +C (15) 2 bd2 bd4 gd2 L C = C (16) 3 gd4 ConsideringC approximatelyzero,thevoltage-transferfunctioncanbewrittenas 3 gm gm ω V (s) ∼= 1 3 V (s)−V (s) 2 (17) out gds +gds gm +sC gs1 gs2 s+ω 2 4 (cid:4)(cid:2) 3 1(cid:3) (cid:5) 2 whereω isgivenas 2 gds +gds ω = 2 4 (18) 2 C 2 The pole ω determines the cut-off frequency of the amplifier and is also called as ω . 2 −3dB Assumingthat gm gds +gds 3 ≫ 2 4 (19) C C 1 2 thenthefrequencyresponseofthedifferentialamplifierreducesto V (s) gm ω out ∼ 1 2 = (20) V (s)−V (s) gds +gds s+ω in1 in2 (cid:2) 2 4(cid:3)(cid:2) 2(cid:3) This first-order analysis leads to a single pole at the output given by −(gds + gds )/C . 2 4 2 Some zeroes occur due to C , C and C , but they can be ignored in this analysis. gd1 gd2 gd4 The gain-bandwidth product (GBW), which is the equal to the unity-gain frequency, can be expressedas GBW = A ·ω (21) vo −3dB The slew-rate (SR) performance of the CMOS differential amplifier depends the value of I ref andthecapacitancefromtheoutputnodetoacgroundandisgivenby I ref SR = (22) C where C is the total capacitance connected to the output node (approximated by C in our 2 analysis). Otherimportantspecificationsfortheelectricalbehaviorofthedifferentialamplifierincludes power dissipation P = I ·(V −V ) and total gate area, calculated as the sum of the diss ref DD SS productofgatewidthandlenghtofalltransistorsthatcomposethecircuit: Area = ∑W ·L (23) i i i All analog design has a target fabrication technology and a device type, in which the set of transistor model parameters is unique. These parameters determines the electrical characteristics-suchasdraincurrent,gatetransconductanceandoutputconductance-ofthe active devices that are part of the circuit. The specifications described before are function of theseparameters,togetherwithWandL. Sincetheparametersarefixedforagivenfabrication