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Scilab Textbook Companion for Digital Principals And Applications by DP Leach And AP Malvino PDF

217 Pages·2016·0.95 MB·English
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Scilab Textbook Companion for Digital Principals And Applications by D. P. Leach And A. P. Malvino1 Created by Kapu Venkat Sayeesh B.Tech (pursuing) Electronics Engineering NIT, Warangal College Teacher S.K.L.V Sai Prakash Cross-Checked by Giridharan, IITB July 30, 2019 1Funded by a grant from the National Mission on Education through ICT, http://spoken-tutorial.org/NMEICT-Intro. ThisTextbookCompanionandScilab codes written in it can be downloaded from the ”Textbook Companion Project” section at the website http://scilab.in Book Description Title: Digital Principals And Applications Author: D. P. Leach And A. P. Malvino Publisher: Tata McGraw - Hill, New Delhi Edition: 6 Year: 2006 ISBN: 0-07-060175-5 1 Scilab numbering policy used in this document and the relation to the above book. Exa Example (Solved example) Eqn Equation (Particular equation of the above book) AP Appendix to Example(Scilab Code that is an Appednix to a particular Example of the above book) Forexample, Exa3.51meanssolvedexample3.51ofthisbook. Sec2.3means a scilab code whose theory is explained in Section 2.3 of the book. 2 Contents ListofScilabCodes 4 1 Digital Principles 6 2 Digital Logic 7 3 Combinational Logic Circuits 25 4 Data processing circuits 43 5 Number Systems and Codes 52 6 Arithmetic Circuits 66 7 Clocks and Timing Circuits 90 8 Flip Flops 105 9 Registers 114 10 Counters 122 11 Design of Sequential Circuit 138 12 D to A Conversion and A to D conversion 145 3 13 Memory 151 14 Digital Integrated circuits 153 15 Applications 156 16 A Simple Computer Design 161 4 List of Scilab Codes Exa 1.1 Finding duty cycle . . . . . . . . . . . . . . 6 Exa 1.2 Maximum decimal count for a counter . . . 6 Exa 2.1 7404 waveform . . . . . . . . . . . . . . . . 7 Exa 2.2 7404 waveform . . . . . . . . . . . . . . . . 9 Exa 2.3 truth table for given figure . . . . . . . . . . 12 Exa 2.4 truth table for given figure . . . . . . . . . . 12 Exa 2.9 proving two circuits are logically equal . . . 13 Exa 2.10 truth table for NOR NOR circuit . . . . . . 14 Exa 2.11 timing diagram for NOR NOR . . . . . . . 14 Exa 2.12 proving two circuits are logically equal . . . 18 Exa 2.13 truth table for NAND NAND circuit . . . . 19 Exa 2.14 timing diagram for NAND NAND circuit . . 19 Exa 2.15 detecting all bits low in a register . . . . . . 23 Exa 3.1 Boolean Algebra . . . . . . . . . . . . . . . 25 Exa 3.2 Boolean Algebra . . . . . . . . . . . . . . . 25 Exa 3.3 Testing a circuit using logic clip . . . . . . . 26 Exa 3.4 Sum of Products . . . . . . . . . . . . . . . 27 Exa 3.5 Boolean Algebra . . . . . . . . . . . . . . . 28 Exa 3.6 Gives a simplified Boolean equation . . . . . 29 Exa 3.7 simplest logic for given Truth table . . . . . 29 Exa 3.8 simplest logic for given logic equation . . . . 30 Exa 3.9 Product of sums . . . . . . . . . . . . . . . 30 Exa 3.10 sop for the karnaugh map . . . . . . . . . . 32 Exa 3.11 POS form of karnaugh map . . . . . . . . . 32 Exa 3.12 POS form of karnaugh map . . . . . . . . . 33 Exa 3.13 Quine Mc clusky method . . . . . . . . . . . 33 Exa 3.14 Dynamic hard . . . . . . . . . . . . . . . . . 37 Exa 4.1 4 to 1 mux using 2 to 1 mux . . . . . . . . . 43 5 Exa 4.2 Realizing boolean equation using 8 to 1 mux 43 Exa 4.3 32 t0 1 mux using 16 to 1 and 2 to 1 muxes 46 Exa 4.4 74154 IC y12 . . . . . . . . . . . . . . . . . 46 Exa 4.7 realizingbooleanequationusing3to8decoder 47 Exa 4.8 current in LED . . . . . . . . . . . . . . . . 48 Exa 4.9 whichLEDlightsupforgiveninputconditions 48 Exa 4.10 output of 74147 when button 6 is pressed . . 49 Exa 4.11 priority encoder . . . . . . . . . . . . . . . . 50 Exa 5.1 Binary to decimal conversion . . . . . . . . 52 Exa 5.2 Binary to decimal conversion . . . . . . . . 54 Exa 5.3 decimal equivalent of 2 Mb . . . . . . . . . . 56 Exa 5.4 Decimal to binary conversion . . . . . . . . 57 Exa 5.5 Binary number having all ones . . . . . . . . 58 Exa 5.6 Decimal to binary conversion . . . . . . . . 59 Exa 5.7 binary to hexadecimal . . . . . . . . . . . . 60 Exa 5.8 hexadecimal to decimal . . . . . . . . . . . . 61 Exa 5.9 decimal to hexadecimal and binary . . . . . 62 Exa 5.10 decimal to hexadecimal and binary . . . . . 63 Exa 5.11 decimal to hexadecimal and binary . . . . . 64 Exa 6.1 8bit binary adder . . . . . . . . . . . . . . . 66 Exa 6.2 16 bit binary adder . . . . . . . . . . . . . . 68 Exa 6.3 first generation microcomputers addition . . 69 Exa 6.4 binary subtraction . . . . . . . . . . . . . . 71 Exa 6.5 adding 8 bit unsigned numbers . . . . . . . 73 Exa 6.6 subtraction of unsigned numbers . . . . . . 76 Exa 6.7 overflow case . . . . . . . . . . . . . . . . . 78 Exa 6.8 2s compliment . . . . . . . . . . . . . . . . . 80 Exa 6.9 2s compliment . . . . . . . . . . . . . . . . . 83 Exa 6.10 2s compliment subtraction . . . . . . . . . . 85 Exa 6.12 final carry in a CLA . . . . . . . . . . . . . 88 Exa 7.1 clock cycle time . . . . . . . . . . . . . . . . 90 Exa 7.2 maximum clock frequency . . . . . . . . . . 90 Exa 7.3 frequency limits of the clock . . . . . . . . . 91 Exa 7.4 Schmitt trigger . . . . . . . . . . . . . . . . 93 Exa 7.5 frequency of oscillation for 555 timer . . . . 94 Exa 7.6 finding Ra and C in 555 timer circuit . . . . 94 Exa 7.7 output pulse width for the timer . . . . . . 95 6 Exa 7.8 value of C necessary to change pulse width to given values . . . . . . . . . . . . . . . . . . 96 Exa 7.9 monostable multivibrator . . . . . . . . . . 96 Exa 7.10 74123 . . . . . . . . . . . . . . . . . . . . . 100 Exa 7.11 finding timing capacitor values . . . . . . . 103 Exa 8.4 RS flipflop . . . . . . . . . . . . . . . . . . . 105 Exa 8.5 positive edge triggred RS flip flop . . . . . . 106 Exa 8.6 negative edge triggred RS flip flop . . . . . . 106 Exa 8.7 T flip flop . . . . . . . . . . . . . . . . . . . 107 Exa 8.9 JK master slave . . . . . . . . . . . . . . . . 107 Exa 8.10 fictitious flip flop excitation table . . . . . . 110 Exa 8.12 state transition diagram for given circuit . . 112 Exa 8.13 D flip flop to RS flip flop . . . . . . . . . . . 113 Exa 9.1 shift register serial input . . . . . . . . . . . 114 Exa 9.2 shift register serial input and output graph . 115 Exa 9.4 54164 shift register . . . . . . . . . . . . . . 120 Exa 9.5 54164 shift register . . . . . . . . . . . . . . 120 Exa 9.8 74ls174 . . . . . . . . . . . . . . . . . . . . . 121 Exa 9.9 7495A . . . . . . . . . . . . . . . . . . . . . 121 Exa 10.1 ripple counter clock frequency . . . . . . . . 122 Exa 10.2 number of flip flops required to construct a counter . . . . . . . . . . . . . . . . . . . . 122 Exa 10.3 Output waveforms for a 7493A connected as a mod 16 counter . . . . . . . . . . . . . . . 124 Exa 10.5 Expression for AND gate connected to the leg of OR gate that drives clock input to flip flop Qd in 74193 . . . . . . . . . . . . . . . . . . 126 Exa 10.6 Expression for 4 input AND gate connected to the leg of OR gate that conditions the J and K inputs to the Qd flip flop in a 74191 . 127 Exa 10.7 number of flip flops required to construct a counter . . . . . . . . . . . . . . . . . . . . 127 Exa 10.8 what modulus counters can be constructed with given number of flip flops e . . . . . . . 128 Exa 10.9 mod 6 counter . . . . . . . . . . . . . . . . . 128 Exa 10.10 Expression for a gate to decode count 8 in a 7492A . . . . . . . . . . . . . . . . . . . . . 132 Exa 10.12 mod 12 counter . . . . . . . . . . . . . . . . 132 7 Exa 10.13 4 bit binary counter presettable . . . . . . . 133 Exa 10.14 self correcting modulo 6 counter . . . . . . . 135 Exa 10.15 sequence generator . . . . . . . . . . . . . . 137 Exa 11.1 synchronous sequential logic circuit . . . . . 138 Exa 11.2 vending machine . . . . . . . . . . . . . . . 140 Exa 11.5 Reducing state transition diagrams . . . . . 141 Exa 11.6 asynchronous sequential circuit . . . . . . . 142 Exa 11.7 asynchronoussequentialcircuitprobleminop- eration . . . . . . . . . . . . . . . . . . . . . 143 Exa 11.8 asynchronous sequential circuit . . . . . . . 144 Exa 12.1 binary equivalent weight of each bit in a 4bit system . . . . . . . . . . . . . . . . . . . . . 145 Exa 12.2 5 bit resistive divider . . . . . . . . . . . . . 146 Exa 12.3 5 bit ladder . . . . . . . . . . . . . . . . . . 146 Exa 12.4 5 bit ladder . . . . . . . . . . . . . . . . . . 147 Exa 12.5 5 bit ladder . . . . . . . . . . . . . . . . . . 147 Exa 12.6 5 bit ladder . . . . . . . . . . . . . . . . . . 148 Exa 12.8 DAC0808 . . . . . . . . . . . . . . . . . . . 148 Exa 12.9 resolution of 9 bit D to A . . . . . . . . . . 149 Exa 12.10 resolution . . . . . . . . . . . . . . . . . . . 149 Exa 12.11 counter type A to D converter . . . . . . . . 149 Exa 12.13 10 bit A to D converter . . . . . . . . . . . 150 Exa 13.2 structure of binary address . . . . . . . . . . 151 Exa 13.3 decimalandhexadecimaladdressforthegiven binary address . . . . . . . . . . . . . . . . 151 Exa 14.1 diode forward or reverse . . . . . . . . . . . 153 Exa 14.2 Diode current . . . . . . . . . . . . . . . . . 154 Exa 14.3 current in the given circuit . . . . . . . . . . 154 Exa 14.4 n channel MOSFET inverter . . . . . . . . . 155 Exa 15.1 Timing of a six digit display . . . . . . . . . 156 Exa 15.4 Basic frequency counter . . . . . . . . . . . 157 Exa 15.5 4 decimal digit frequency counter . . . . . . 157 Exa 15.6 instrument to measure time period . . . . . 158 Exa 15.9 ADC0804 . . . . . . . . . . . . . . . . . . . 158 Exa 15.10 ADC3511 . . . . . . . . . . . . . . . . . . . 159 Exa 15.11 ADC3511 . . . . . . . . . . . . . . . . . . . 160 Exa 15.12 ADD3501 . . . . . . . . . . . . . . . . . . . 160 Exa 16.1 size of PC IR ACC MAR MDR . . . . . . . 161 8 Exa 16.6 Number of clock cycles needed to execute a program . . . . . . . . . . . . . . . . . . . . 162 9

Description:
List of Scilab Codes. 4. 1 Digital Principles. 6. 2 Digital Logic. 7. 3 Combinational Logic Circuits. 25. 4 Data processing circuits. 43. 5 Number Systems
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