Tampereen teknillinen yliopisto. Julkaisu 483 Tampere University of Technology. Publication 483 Christian Panis Scalable DSP Core Architecture Addressing Compiler Requirements Thesis for the degree of Doctor of Technology to be presented with due permission for public examination and criticism in Tietotalo Building, Auditorium TB104, at Tampere University of Technology, on the13th of August 2004, at 12 o(cid:146)clock noon. Tampereen teknillinen yliopisto - Tampere University of Technology Tampere 2004 ISBN 952-15-1205-9 ISSN 1459-2045 Abstract This thesis considers the definition and design of an embedded configurable DSP (Digital Signal Processor) core architecture and will address the necessary requirements for developing an optimizing high-level language compiler. The introduction provides an overview of typical DSP core architectural features, briefly discusses the currently available DSP cores and summarizes the architectural aspects which have to be considered when developing an optimizing high-level language compiler. The introduction is followed by a total of 12 publications which outline the research work carried out while providing a detailed description of the main core features and the design space exploration methodology. Most of the research work focuses on architectural aspects of the configurable RISC (Reduced Instruction Set Computer) DSP core based on a modified Dual-Harvard load-store architecture. Due to increasing application code size and the associated configuration aspect the use of automatic code generation by a high-level language compiler is required. To generate code efficiently requires that the architectural aspects be considered as early as definition stage. This results in an orthogonal instruction set architecture with simple issue rules. Architectural features are introduced to reduce area consumption and power dissipation to fulfill requirements of SoC (System-on-Chip) and SiP (System-in-Package) applications and close the gap between dedicated hardware implementations and software based system solutions. Code density has a significant influence on the area of the DSP sub-system, thus xLIW (scalable Long Instruction Word) is introduced. An instruction buffer allows the reduction of power dissipation during execution of loop-centric DSP algorithms. Simple issue rules and exhaustive predicated execution feature enable efficient cycle and power execution of control code. The scalable DSP core architecture introduced herein allows parameterization of the main architectural features to application specific requirements. To make use of this feature it is necessary to analyze the requirements of the application. This thesis introduces a design space exploration methodology based on a C-compiler and a cycle-true instruction set simulator. A unique XML-based configuration file is used to reduce the implementation and validation effort for configuring the tool-chain, updating documentation and for automatic generation of parts of the VHDL-RTL core description. II III Preface The research work described in this thesis was carried out during 1999-2004 in Infineon Technologies Austria and in the Institute of Digital and Computer Systems at the Tampere University of Technology in Tampere, Finland. I will like to express my deepest gratitude to my thesis advisor, Prof. Jari Nurmi. He introduced and guided me carefully through the scientific world. Jari hosted me during my stays at the university in Tampere and warmed the cockles of my heart in the sometimes cold Finland. Prof. Jarmo Takala as head of the Institute of Digital and Computer Systems supported my study work and along with Lasse Harju and Timo Rintakoski ensured me a warm and pleasant working environment during my time at TUT. A note of gratitude goes out to Prof. Lars Wanhammar and Dr. Mika Kuulusa for reviewing my thesis and supporting me with imperative feedback. Defining and developing a new DSP core when considering the approach of Hardware and Software Co-Definition can only be done with a competent and enthusiastic team. Therefore I would like to express my deepest thanks to the xDSPcore team which contributed excellent work during the long period. Many thanks to Prof. Andreas Krall from Vienna University of Technology who influenced the xDSPcore architecture and considered aspects relevant when developing an optimizing C-compiler and to Karl V(cid:246)gler and Ulrich Hirnschrott who developed the main parts of the C-compiler backend and supporting my thesis by contributing benchmarks and analysis results alongside many productive discussions. Many thanks also to the internship and masters students who contributing to the xDSPcore research project including Pierre Elbischger, Gunther Laure, Wolfgang Lazian, Raimund Leitner, Michael Bramberger and many more. During my time in Infineon Technologies I had the pleasure to meet many amazing people which led to a plethora of a lot of fruitful discussions again representative, many thanks to Herbert Zojer who supported the development of an innovative DSP core architecture, to Prof. Lajos Gazsi, Fellow of Infineon Technologies and Dr. S(cid:246)hnke Mehrgardt the CTO of Infineon Technologies who guided the development team inside the company. I would like to express my thanks to Dr. Franz Dielacher, Manfred Haas and Reinhard Petschacher at Infineon Technologies Austria and Prof. Herbert Gr(cid:252)nbacher and Erwin Ofner at Carithian Tech Institute who enabled me to finalize my research work. IV In addition I would like to express my thanks to Prof. Tobias G. Noll and Volker Gierenz at RWTH Aachen who assisted the project from the beginning with their technical expertise. The research was financially supported by Infineon Technologies Austria, the European Commission with the project SoC-Mobinet (IST-2000-30094) and the Carinthian Tech Institute who hosted me in the last two years. Many thanks. Most of all I would like to express my deepest gratitude to my parents Maria and Herbert Panis and brother Peter who supported me unrelentingly throughout the long time period with their love. Only through their support was it possible for me to complete my studies in Tampere, Finland. Tampere, August 2004 Christian Panis V Table of Contents 1 Introduction.....................................................................................................................2 1.1 Motivation...............................................................................................................2 1.2 Methodology...........................................................................................................3 1.3 Goals.......................................................................................................................4 1.4 Outline of Thesis.....................................................................................................4 2 DSP Specific Features.....................................................................................................7 2.1 Introduction.............................................................................................................7 2.2 Saturation................................................................................................................7 2.3 Rounding.................................................................................................................9 2.4 Fixed-Point, Floating-Point...................................................................................10 2.5 Hardware Loops....................................................................................................12 2.6 Addressing Modes................................................................................................13 2.7 Multiple Memory Banks.......................................................................................18 2.8 CISC Instruction Sets............................................................................................19 2.9 Orthogonality........................................................................................................20 2.10 Real-Time Requirements......................................................................................21 3 DSP cores......................................................................................................................23 3.1 Design Space.........................................................................................................23 3.2 Architectural Alternatives.....................................................................................31 3.3 Available DSP Core Architectures.......................................................................37 3.4 xDSPcore..............................................................................................................49 4 High Level Language Compiler Issues.........................................................................51 4.1 Coding Practices in DSP(cid:146)s....................................................................................51 VI 4.2 Compiler Overview...............................................................................................59 4.3 Requirements........................................................................................................62 4.4 HLL-Compiler Friendly Core Architecture..........................................................69 5 Summary of Publications..............................................................................................73 5.1 Architectural Aspects of Scalable DSP Core........................................................73 5.2 Design Space Exploration.....................................................................................76 5.3 Author(cid:146)s Contribution to Published Work............................................................77 6 Conclusion....................................................................................................................81 6.1 Main Results.........................................................................................................81 6.2 Future Research....................................................................................................84 7 References.....................................................................................................................89 VII List of Publications This thesis is split into two parts with the first containing an introduction into Digital Signal Processor architectures and the second part a reprint of the publications listed below. [P1] C. Panis, J. Nurmi, (cid:147)xDSPcore - a Configurable DSP Core(cid:148), Technical Report 1-2004, Tampere University of Technology, Institute of Digital and Computer Systems, Tampere, Finland, May 2004. [P2] C. Panis, R. Leitner, H. Gr(cid:252)nbacher, J. Nurmi, (cid:147)xLIW (cid:150) a Scaleable Long Instruction Word(cid:148), in Proceedings The 2003 IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 25-28, 2003, pp. V69-V72. [P3] C. Panis, R. Leitner, H. Gr(cid:252)nbacher, J. Nurmi, (cid:147)Align Unit for a Configurable DSP Core(cid:148), in Proceedings on the IASTED International Conference on Circuits, Signals and Systems (CSS 2003), Cancun, Mexico, May 19-21, 2003, pp. 247-252. [P4] C. Panis, M. Bramberger, H. Gr(cid:252)nbacher, J. Nurmi, (cid:147)A Scaleable Instruction Buffer for a Configurable DSP Core(cid:148), in Proceedings of 29th European Solid State Conference (ESSCIRC 2003), Estoril, Portugal, September 16-18, 2003, pp. 49-52. [P5] C. Panis, H. Gr(cid:252)nbacher, J. Nurmi, (cid:147)A Scaleable Instruction Buffer and Align Unit for xDSPcore(cid:148), IEEE Journal of Solid-State Circuits, Volume 35, Number 7, July 2004, pp. 1094-1100. [P6] C. Panis, U. Hirnschrott, A. Krall, G. Laure, W. Lazian, J. Nurmi, (cid:147)FSEL (cid:150) Selective Predicated Execution for a Configurable DSP Core(cid:148), in Proceedings of IEEE Annual Symposium on VLSI (ISVLSI-04), Lafayette, Louisiana, USA, February 19-20, 2004, pp. 317-320. [P7] C. Panis, G. Laure, W. Lazian, H. Gr(cid:252)nbacher, J. Nurmi, (cid:147)A Branch File for a Configurable DSP Core(cid:148), in Proceedings of the International Conference on VLSI (VLSI(cid:146)03), Las Vegas, Nevada, USA, June 23-26, 2003, pp. 7-12. [P8] C. Panis, R. Leitner, J. Nurmi, (cid:147)A Scaleable Shadow Stack for a Configurable DSP Concept(cid:148), in Proceedings The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC), Calgary, Canada, June 30-July 2, 2003, pp. 222-227. VIII [P9] C. Panis, J. Hohl, H. Gr(cid:252)nbacher, J. Nurmi, (cid:147)xICU - a Scaleable Interrupt Unit for a Configurable DSP Core(cid:148), in Proceedings 2003 International Symposium on System-on- Chip (SOC(cid:146)03), Tampere, Finland, November 19-21, 2003, pp. 75-78. [P10] C. Panis, G. Laure, W. Lazian, A. Krall, H. Gr(cid:252)nbacher, J. Nurmi, (cid:147)DSPxPlore (cid:150) Design Space Exploration for a Configurable DSP Core(cid:148), in Proceedings International Signal Processing Conference (GSPx), Dallas, Texas, USA, March 31- April 3, 2003, CD-ROM. [P11] C. Panis, U. Hirnschrott, G. Laure, W. Lazian, J. Nurmi, (cid:147)DSPxPlore - Design Space Exploration Methodology for an Embedded DSP Core(cid:148), in Proceedings of the 2004 ACM Symposium on Applied Computing (SAC 04), Nicosia, Cyprus, March 14-17, 2004, pp. 876-883. [P12] C. Panis, A. Schilke, H. Habiger, J. Nurmi, (cid:147)An Automatic Decoder Generator for a Scaleable DSP Architecture(cid:148), in Proceedings of the 20th Norchip Conference (Norchip(cid:146)02), Copenhagen, Denmark, November 11-12, 2002, pp. 127-132.