DESIGN PORT AND OPTIMIZATION OF A HIGH-SPEED SAR ADC COMPARATOR FROM 65NM TO 0.11pM MASSACHUSETTS INSTITUTE by OF TECHqOLOGY JUN 2 1 2011 Nora Iordanova Micheva LIBRARIES B.S. Electrical Engineering and Computer Science, MIT, 2010 Submitted to the Department of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degree of Master of Engineering in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology ARCHNES May 2011 Copyright Massachusetts Institute of Technology. All rights reserved. The author hereby grants to MIT permission to reproduce and to distribute publicly paper and electronic copies of this thesis document in whole and in part in any medium now known or hereafter created. Author: Department of Electrical Engineering and Computer Science May 17, 2011 Certified by: Charles G. Sodini, LeBel Professor of Electrical Engineering Thesis Supervisor Certified by: Doris Lin, Design Engineer, Analog Devices Inc. Thesis Co-Supervisor Accepted by: Dr. Christopher J. Terman Chairman, Masters of Engineering Thesis Committee DESIGN PORT AND OPTIMIZATION OF A HIGH-SPEED SAR ADC COMPARATOR FROM 65NM TO 0.11IM by Nora Micheva Submitted to the Department of Electrical Engineering and Computer Science May 15, 2011 In Partial Fulfillment of the Requirements for the Degree of Master of Engineering in Electrical Engineering and Computer Science ABSTRACT As the world continues to do more and more of its signal processing digitally, there is an ever increasing need for high speed high precision signal processors in consumer applications such as digital photography. Technological progress in CMOS fabrication has allowed chips to be made on nano scale processes, but this still comes at a steep price. Especially in chips for which analog components are a priority over digital components, some of the benefits of using nano scale processes diminish, such as smaller area. In these cases, it is worth investigating whether the same performance can be achieved with larger feature size, and therefore, cheaper processes. To that end, a three-stage comparator circuit for use in a digital camera SAR ADC has been ported from its original 65nm process to a 0.11ptm process. Its design has been analyzed and performance presented here. Additionally, an alternative latch-only architecture for the comparator has been designed and analyzed. In 0.11pm the three-stage comparator operates at the same speed, 13% lower RMS noise contributing 0.9 bits difference, and 11% higher power than the original in 65nm. More noteworthy, the 0.11pm latch-only comparator operates at 40% higher speed, equivalent noise, and 72% lower power. ACKNOWLEDGMENTS My thesis was sponsored by MIT and Analog Devices, Inc. through the VI-A program, which allowed me the opportunity to work on a real-world industry project while at the same time obtaining a Master's degree. I would like to especially thank my advisor at ADI, Doris Lin. She was there for me every step of the way, providing patient guidance and support when I needed it the most. I think she is a great mentor and I will remember my time at ADI fondly. I would also like to thank my faculty advisor at MIT, Professor Charles Sodini. He provided guidance to me even before I began working on my M.Eng., and offered to be my supervisor despite his hectic schedule. I am thankful for his advice on which direction to take in my thesis, and his insistence on quality work. I will take these lessons with me in my career going forth. At ADI I would first like to thank Ron Kapusta, whose work this thesis is based on, and who first recruited me to the group. His intuitive explanations always made the difficult seem easy to me. I would also like to thank the design engineers who always welcomed my questions no matter how silly they were: Henry Zhu, Junhua Shen, Steve Decker, Dave Roberts, Mark Sayuk, and Katsu Nakamura. I would like to thank the lunch cohort (Mitushi, Yero, Neal, Ned, Jason, Vivek, Paul) for making me really feel like a part of the team, and Mark Robinson for his cheerful conversations with me. While he wasn't on the team, I'd like to give special thanks to Benjamin Walker, the VI-A representative from ADI. He made me feel at home from day one, and always took special time to check up on me. I am grateful for all the new EE concepts I learned from him during our weekly meetings. At MIT, I would like to thank Anne Hunter for having her door always open to me, no matter what trouble I had to bring to her. She had faith in me four years ago when I decided to become course 6 and was nervous about all the catching up I had to do, and she's still there for me now. I'd also like to thank Professor Joel Schindall, my department adviser and director in the Gordon Program, for being a mentor to me all this time in course 6 and in GEL, in which I learned so much about what I'm really capable of. Finally, I would like to thank my mom, dad, Peri, and Simon for loving and supporting me through it all. MIT has been quite a journey, and I am certain that I couldn't have done it without them. My mom and dad for trusting that I could do anything I put my mind to even when I didn't, Peri for being the best little sister I could ever dream to have, and Simon for loving me unconditionally and taking in stride everything this journey took us to. Thank you! TABLE OF CONTENTS Chapter 1: Introduction................................................................................................................................ 6 1.1 Mo tivation.................................................................................................................................... 6 1.2 Fundam entals and Basics of Operation ........................................................................... 8 1.2.1 A peek into SAR A DCs ................................................................................................ 8 1.2.2 Com parator Design Fundam entals ...................................................................... 10 1.3 State of the A rt.......................................................................................................................... 12 1.4 Specifications of Interest................................................................................................... 13 Chapter 2: Characterization of 65nm vs 0.11um Process.................................................................15 2.1 Transconductance ................................................................................................................... 16 2.2 Output Resistance....................................................................................................................18 2.3 Parasitic Capacitances........................................................................................................ 20 Chapter 3: 65nm Com parator Topology A nalysis...............................................................................21 3.1 Stage 1: Integrator................................................................................................................... 21 3.2 Stage 2: Pream plifier ......................................................................................................... 26 3.3 Stage 3: Latch............................................................................................................................30 Chapter 4: Design Port................................................................................................................................ 32 4.1 Design Port + Perform ance of Stage 1.......................................................................... 34 4.2 Design Port of Stage 2 and Performance of Stages 1 + 2.......................................... 37 4.3 Design Port of Stage 3 and Performance of All Stages Together ........................... 39 4.4 Results......................................................................................................................................... 39 Chapter 5:N ew Architecture ..................................................................................................................... 41 Overall Results.................................................................................................................................42 Chapter 6: Conclusion and Future W ork ........................................................................................... 43 Chapter 7: Appendix.................................................................................................................................... 44 7.1 Testing for Speed/Accuracy: Hysteresis Analysis...................................................... 44 7.2 N oise A nalysis: SpectreRF...................................................................................................447 References ...................................................................................................................................................... 50 [4] TABLE OF FIGURES Figure 1: Example of a current 12-bit CCD Signal Processor [3] on the market by Analog Devices. The ADC is highlighted in with a star.............................................................................................................................. 6 Figure 2: SAR ADC Architecture [2]................................................................................................................................. 8 Figure 3: A representative 4-bit SAR ADC Architecture (adapted from [2])................... 9 Figure 4: Close-up of 4-bit SAR function given VSH=0.6V.............................................................................. 10 Figu re 5 : Co m p arator........................................................................................................................................................... 1 0 Figu re 6: D ynam ic Latch [7]..............................................................................................................................................11 Figure 7: Small-signal MOSFET model..........................................................................................................................15 Figure 8: Transconductance versus current for the four devices; W=1pm for all, L= minimum length; ....................................................................................................................................................................................................... 1 6 Figure 9: Ron versus width for 0.11 tm NMOS device....................................................................................... 19 F igu re 1 0: 6 5 n m Stag e 1.................................................................................................................................................2 1 Figure 11: Model of input and cascode transistor on one side of the first stage, including each noise cu rre n t ....................................................................................................................................................................................... c2 5 F igu re 12: 6 5 n m Stage 2 ................................................................................................................................................. 2 6 Figure 13: Model of Stage 2's cross-coupled devices..........................................................................................27 Figure 14: Stage 2 Close-up of Cross-coupled loads................................................................................. 29 F igu re 1 5: 6 5 n m Stage 3 ................................................................................................................................................. 3 0 Figure 16: 0.11 m Comparator.......................................................................................................................................32 Figure 17: Final Dimensions of 0.11ptm Stage 1......................................................................................... 34 Figure 18: Close-up of Switches in 0.11 m Stage ................................................................................................ 35 Figure 19: Close-up of Stage 1 input-pair in 0.11tm......................................................................................... 35 Figure 20: Resistances looking up and down between the input and cascode devices of Stage 1......36 Figure 21: Final Dimensions of Stage 2 in 0.11um................................................................................... 37 F igu re 2 2: Stag e 3 .................................................................................................................................................................. 3 9 Figure 23: New Latch-only Architecture......................................................................................................................41 Figure 24: Implementation of Latch-Only Architecture [8]........................................................................... 41 Figure 25: 640pV/-20V Hysteresis test for three comparator types ..................................................... 45 Figure 26: 20mV/-160[pV Hysteresis test for three comparator types ..................................................... 46 Figure 27: SpectreRF pss analysis .................................................................................................................................. 47 Figure 28: SpectreRF pnoise analysis ..................................................................................................................... 49 [5] CHAPTER 1: INTRODUCTION 1.1 MOTIVATION Nano scale CMOS technologies provide many benefits in the implementation of today's highly digital circuits, especially in consumer electronics. Digital circuitry follows Moore's law [1] in that moving to a smaller feature size process means more digital components can fit in the same area. Also, smaller devices offer higher gate speed at lower power dissipation digital circuitry. Analog circuits, however, do not necessarily shrink as many designs do not use or allow for minimum length devices. Therefore, in chips in which analog components are more emphasized, some of the benefits of smaller scale technologies such as a reduced chip area are no longer as relevant, and are therefore offset by drawbacks such as higher expense. This makes it worthwhile to investigate implementation of the circuits in larger feature size processes. The setting of this thesis is the field of high-speed high-precision signal processors for digital camera and camcorder applications. One of the major components of these signal weF processors is the high-speed ADC EtR -0 ABD 992V0AoEr (analog-to-digital converter, see CCDIN CoS VGA OUT star outline in Fig. 1). Several 1T=462dd 3VI NPUT DC LK IVOUTPUT REG different types of ADC's are INTERCNLAO+CLcK oSmmonly used in signal AG ' ......f. 4.# ............ VHTOVORIZONTAL DRIVERS GENERATOR SL processing applications including H1TERONS ECK VIA TOV S( 3-LEVEL) 19 X1 OX SOATA V. TO V1D16G SNYC~ Hflash, pipeline, and Successive Approximation Register (SAR) apO?, GPOS [2]. Flash ADCs are fast parallel Figure .: Example of' a current 12-bit CCg Signal Processor 31 on the market by Analog Devices. The ADC is highlighted in with a star. converters but they have a drawback in that for an N-bit flash ADC, 2N-1 comparators are necessary, thus power and area becomes an issue. Pipeline ADCs are very good for high- speed applications, but their power consumption is often an issue [2]. While the high-speed ADC of choice for the Digital Imaging Group has traditionally been a pipeline ADC, with its transition from 0.18[im to a 65nm CMOS fabrication process, the group began investigating the use of SAR ADCs instead. SAR ADCs tend to consume less power than pipelined ADCs at the cost of speed, but due to the inherent increase in gate speed of the 65nm process node, this trade-off of speed for power was able to be circumvented, and the same spec was achieved by the group. Also, unlike pipeline ADCs, SAR ADCs do not require an amplifier and are thus better suited for smaller process devices with intrinsically lower gain. For this reason, the group decided to use the SAR architecture for its 65nm ADC. This thesis describes the design port of a comparator for a SAR ADC in digital still camera and camcorder applications, from the 65nm to 0.11pm process node. The two processes have similar characteristics and both operate off a 1.2V supply. Hence, 0.11im seems like a cheaper alternative to 65nm for chips in which there is less emphasis on digital circuitry, because the area taken by the analog components will be roughly the same. For this reason, porting strategies that maintain the 65nm comparator's performance while moving to the 0.11ptm process are investigated here. Furthermore, a different architecture from the one used in 65nm is explored and its relative performance is presented. The group has never utilized a 0.11ptm process before, so this will be the company's first investigation to transition the design of their high speed SAR ADC comparator from 65nm to 0.11m. The SAR ADC is a 14-bit converter with two redundant bit decisions, for a total of 16 bit decisions. The first 5 MSBs (most significant bits) are decided by an auxiliary flash ADC, leaving 11 decisions for the comparator to arbitrate. The comparator designed by Analog Devices comprised of three stages: two preamplifier stages, followed by a dynamic latch. While the dynamic latch can make comparator decisions on its own, the preamplifiers increase the signal to overcome offset in the comparator. The preamplifiers also shield the input signal from charge kickback in the latch, defined the charge that is "kicked back" to the inputs through Cgd of the input pairs when the latch regenerates. While this doesn't have negative repercussions for all input signals, the inputs in this case come from a capacitive DAC used for sampling that is sensitive to this charge kickback. 1.2 FUNDAMENTALS AND BASICS OF OPERATION 1.2.1 A PEEK INTO SAR ADCs A SAR ADC uses a successive approximation binary search algorithm to get a digital representation of an analog input signal. Fig. 2 shows a simplified representation of a SAR ADC, whose main components are a Track/Hold stage, a SAR logic/register stage, an N-bit digital to analog converter (DAC), and a comparator. Analog in - Track /Hold -+N Comparator vnAC V REF N-bit DAC DigitaI data out N-bit (serial or parallel) Register SAR Logic Figure 2: SAR ADC Architecture [2] Each conversion period consists of two phases: in the first one, the analog signal is tracked and held, and in the second one, the digital output bits are resolved by the SAR logic. Fig. 3 is an example diagram of a four bit SAR ADC using a feedback capacitive DAC. v. -V-IN H S/H T 0 T 0 Reset switch 0bthfbWb b bi b 3bz Successive Approximation Logic Figure 3: A representative 4-bit SAR ADC Architecture (adapted from [21) Let us take an example with the held value being VSH=0. 6V and VREF=1V. After resetting the DAC voltage VDAC=OV, the most significant bit (MSB), b3, is instantiated as 1. This connects the capacitor for the MSB to VREF and makes the DAC voltage to be fed into the comparator to become 0.5*VREF, or O.5V. At the comparator level, this is compared to 0.6V and since it is higher, the comparator outputs a logic '1', which is translated through the successive approximation logic to set b3 to 1 for the remainder of the translation. If the sampled voltage were lower than O.5V, the Reset Switch would be used to reset the capacitors and turn b3 to 0 for the remainder of the cycle. A similar process is used for the remainder of the bits, eventually converging VDAC to VSH. The figure below shows this process in terms of the successive approximation to VSH. VSH= 0.60V 1.00 0.75- m~ 0.50- 00 Time b,=1 b b=0 b,=1 2=0 Figure 4: Close-up of 4-bit SAR function given VSH=0.6V 1.2.2 COMPARATOR DESIGN FUNDAMENTALS High speed comparators are critical in making a high speed SAR ADC, because they are one of the main bottlenecks in the overall speed of the ADC. The comparators used in this application take the difference between V+ and V- and if it is positive (i.e. V+ is larger) VS they output a logic '1', otherwise they output a logic '0'. The speed, V + or a response time in a comparator is defined as the delay between V_ -the time the differential input passes the comparator threshold vs_ voltage and the time the output exceeds the input logic level of the Figure 5: Comparator subsequent stage [4]. One of the simplest forms of a comparator is a two stage compensated op-amp. Compensation of an op-amp often involves the separation of the poles of an op-amp by lowering one pole through the addition of a large capacitor at the output [4]. This form of compensation greatly decreases the speed of op-amps and makes them undesirable for high-speed applications. Even in the uncompensated case, however, the response time is still significantly slow due to other parasitic capacitances, and making this type of comparator inadequate for most high speed applications. [10]