TABLE OF CONTENTS Dedication i Abstract ii Acknowledgements iv List of Illustrations viii List of Tables xi Publications xii CHAPTER 1 INTRODUCTION 1 1.1 Properties of Single Electronic Systems 1 1.2 The Need for Novel Analysis Tools 4 1.3 Breakdown of Work to be Accomplished 4 CHAPTER 2 BACKGROUND 7 2.1 Historical Background 2.1.1 Coulomb Blockade 7 2.1.2 Coulomb Staircase 8 2.1.3 Single Electronic Transistor 10 2.1.4 Further Areas of Research 12 2.2 Fabrication Technologies 2.2.1 Metal-Insulator Technologies 14 2.2.2 Semiconductor Technologies 18 2.3 System Properties 2.3.1 Analogue Systems 22 2.3.2 'Digital' Systems 23 2.3.3 Unanswered Questions 25 2.3.4 The Need for Modelling Tools 26 CHAPTER 3 ANALYSIS OF DEVICE GEOMETRY & CAPACITANCE 27 3.1 The Need for Analytic Capacitance Calculations 3.1.1 Analytic Solution Versus Finite Element Methods 27 3.1.2 Geometrical Idealisations 29 3.2 Analytic Solutions 3.2.1 Spherical Conductor with Dielectric Shell 32 3.2.2 Two Conducting Spheres Surrounded by Dielectric Shells... 33 3.2.3 Two Equal Conducting Spheres 35 3.2.4 Conducting Sphere and Plane 37 — v — 3.3 Comparison of Solutions 3.3.1 Spheres without Dielectric Shells 38 3.3.2 Spheres with Dielectric Shells 42 3.4 Summary of Results 44 CHAPTER 4 THEORETICAL MODELS OF TUNNELLING JUNCTION OPERATION 45 4.1 Tunnelling Junctions - Microscopic model 4.1.1 Derivation of Governing Equations 45 4.1.2 Systems of Tunnelling Junctions 49 4.2 Tunnelling Junctions - Quantum Lengevin Equation 4.2.1 Derivation of Governing Equations 50 4.2.2 Comparison of Thermal and 'Quantum' Fluctuations 51 4.3 Tunnelling Junctions - Phase-Correlation Theory 4.3.1 Derivation of Governing Equations 53 4.3.2 Systems of Tunnelling Junctions 55 4.4 Summary of Tunnelling Junction Theories 56 4.5 Higher Order Processes / Macroscopic Quantum Tunnelling 4.5.1 Macroscopic Quantum Tunnelling in a Single Junction 58 4.5.2 Macroscopic Quantum Tunnelling in Double Junctions 59 4.5.3 Macroscopic Quantum Tunnelling in Extended Systems 62 CHAPTER 5 DEVELOPMENT OF SIMULATION TOOLS FOR SINGLE- ELECTRONIC SYSTEMS 64 5.1 Development through Analysis of Tunnelling Junction Arrays 5.1.1 Reasons For Studying Tunnelling Junction Arrays 65 5.1.2 Equivalent Circuit Model 66 5.1.3 Device Operation, Theoretical Analysis 68 5.1.4 Device Operation, Monte Carlo Modelling 71 5.2 Development through Analysis of Turnstiling Devices 5.2.1 Reasons For Studying Turnstiling Devices 74 5.2.2 Equivalent Circuit Model 75 5.2.3 Turnstile Operation 77 5.2.4 Concept of 'Critical Charges' 79 5.2.5 Device Operation, Linear Programming Approach 80 5.3 General Network Solver & Linear Programming Technique 5.3.1 The Need For General Simulation Tools 84 5.3.2 General Network Solver - Charge Profile Calculation 85 5.3.3 General Network Solver - Critical Charge Calculation 87 5.4 Summary 91 — vi — CHAPTER 6 APPLICATION OF SIMULATION TOOLS TO SINGLE ELECTRONIC SYSTEMS 92 6.1 Tunnelling Junction Arrays 6.1.1 Junction Arrays Under Idealised Conditions 93 6.1.2 Non-Homogeneous Array Systems 95 6.2 Gated Turnstile Devices 6.2.1 Simple Turnstile Devices 106 6.2.2 3-Phase Turnstile Devices 109 6.3 Coupled Junction Arrays 6.3.1 Reasons For Studying Coupled Systems 118 6.3.2 Coupled Tunnelling Junction Arrays 119 6.4 Coupled Gated Turnstiles 6.4.1 Coupled Four-Junction Turnstiles 124 6.4.2 Bit Error Rates in Coupled Turnstiles 130 6.5 Summary 135 CHAPTER 7 CONCLUSIONS AND FURTHER WORK 136 7.1 Conclusions 7.1.1 Fabrication and Geometry 137 7.1.2 Mathematical Models 137 7.1.3 Application to Specific Systems 138 7.2 Further Work 7.2.1 Fabrication and Geometry 139 7.2.2 Mathematical Models 140 7.2.3 Application to Specific Systems 140 APPENDICES A Elementary Stability Analysis of Tunnelling Junction Arrays B Bispherical Coordinate Systems C Results Necessary to Obtain the Capacitance of Two Spherical Conductors D Integral Results Necessary for the Solution of Laplace's Equation in Bispherical Coordinates E Code Structures F Effective Capacitance of Ladder Circuits REFERENCES LIST OF ILLUSTRATIONS 1.1 Equivalent circuit parameters for a double junction system 2 1.2 Comparison of critical parameters for ultrasmall tunnelling junctions 3 2.1 Equivalent circuit parameters for a double junction system 9 2.2 Cross section schematic of an array of double junctions formed by sandwiching a thin conducting film between two bulk electrodes 10 2.3 Energy diagram illustrating the effect of fractional charge on the central electrode of a double junction 11 2.4 Processing steps involved in creating MIM tunnelling junctions 14 2.5 Laterally patterned, squeezed 2DEG in a semiconductor heterostructure, and schematic of its potential landscape 14 2.6 Electron micrograph of lateral, Schottky dot device 15 2.7 Lateral metal-semiconductor-metal, Schottky dot system 16 2.8 Schematic of controlled position, granular structure 16 2.9 Schematic of a double barrier resonant tunnelling device 20 2.10 Circuit schematic of a capacitive single electronic transistor 22 3.1 Electric potential of two aluminium wires on a silicon substrate 28 3.2 Geometrical idealisation of granular tunnelling devices 30 3.3 Schematic of a metal sphere surrounded by a dielectric shell 32 3.4 Bispherical coordinate system 33 3.5 Schematic of two metal spheres surrounded by dielectric shells 34 3.6 Schematic representation of two equivalent metal spheres 35 3.7 Schematic representation of a metal sphere and surface 37 3.8 Two methods of approximating the capacitance between spheres 38 3.9 Capacitance versus intersphere distance for two metallic spheres 39 3.10 Capacitance approximations for two lOnm radius metallic spheres 39 3.11 Capacitance for metallic spheres surrounded by dielectric shells 43 3.12 Boundaries of a lOnm radius sphere and dielectric shell versus distance from the origin plane in a bispherical coordinate system 43 4.1 Equivalent circuit of single tunnel junction 45 4.2 Charge space probability density a for tunnelling junction 48 4.3 Equivalent circuit of tunnel junction with quantum fluctuations 50 Illustrations (cont.) 4.4 Tunnelling rate versus charge predicted by simple microscopic model 52 4.5 Tunnelling rate predicted by quantum Langevin equation (T -> 0) 52 4.6 Equivalent circuit of tunnel junction in series with inductor 53 4.7 Energy diagrams of possible tunnelling processes in a single junction 58 4.8 Illustration of inelastic and elastic Macroscopic Quantum Tunnelling 60 5.1 Equivalent circuit of tunnelling junction array 66 5.2 Schematic of the polarisation caused by a single electron soliton 68 5.3 Equivalent circuit diagram for a gated turnstiling device 75 5.4 Potential of gated turnstile during electron injection/ejection 78 5.5 Thevenin equivalent circuit of tunnel junction and external circuit 79 5.6 Tunnelling events governing the operation of a gated turnstile 82 5.7 Legal turnstiling area in parameter space for a gated turnstile 83 5.8 Equivalent circuit components requiring the matrix Zcon 86 5.9 Equivalent circuit diagrams for possible reduced Zeff matrices 88 6.1 Average soliton concentration in a tunnelling junction array 94 6.2 IV curve for an 8 junction array 96 6.3 IV curves for 10 and 25 junction arrays 96 6.4 Average soliton concentration - array component deviation varied 98 6.5 Energy versus soliton position for an array with single perturbed grounding capacitance 99 6.6 Energy versus soliton position for an array with single perturbed junction capacitance 99 6.7 Array threshold voltage versus capacitance deviation 101 6.8 ditto 102 6.9 ditto 103 6.10 Clocked electrons versus clocking frequency for a gated turnstile 107 6.11 Area of turnstiling operation vs. gate capacitance for simple turnstile 107 6.12 Tunnelling events governing the operation of a three-phase turnstile 110 6.13 Operating area in control parameter space for a three-phase turnstile 111 6.14 Three-phase turnstile, showing time dependence of gating potentials 114 6.15 Graphs of transferred electrons through simple and three-phase turnstiles versus fraction of junction critical frequency 114 6.16 Area of legal turnstiling operation for three-phase device 115 6.17 ditto 116 Illustrations (cont.) 6.18 Tunnelling junction arrays linked by stray capacitance 120 6.19 IV curves for linked arrays of six junctions - temperature varied 120 6.20 IV curves for linked arrays of six junctions - linking strays varied 121 6.21 ditto 121 6.22 Critical charge vs. coupling capacitance for linked six-junction arrays 123 6.23 Four-junction gated turnstiles linked by stray capacitance 125 6.24 Critical charge vs. linking capacitance for identical gated turnstiles 125 6.25 Transferred electrons through two linked, four-junction gated turnstiles versus fraction of junction critical frequency 126 6.26 Operating area in control parameter space for linked gated turnstiles 127 6.27 Bitstream accuracy of coupled four-junction gated turnstiles 131 6.28 ditto 134 6.29 ditto 134 C.1 Metal spheres surrounded by dielectric shells, sitting in a dielectric C-1 E.1 Flow chart of algorithm used to calculate one iteration of tunnelling events in a tunnelling junction array E-3 E.2 Flow chart of algorithm used to calculate multiple iterations of events and bias condition changes in a four-junction turnstile device E-4 E.3 Flow chart of algorithm used to calculate critical charge values of a general network E-7 F.1 Circuit schematic of a C/Co ladder F-1 F.2 Circuit schematic of a C/Cs/C ladder F-1 LIST OF TABLES 2.1 Estimates of tunnelling junction main parameters 8 2.2 Duality transformations relating single electronic devices and Josephson Junction superconducting quantum interferometer devices 24 3.1 Common geometric idealisations of junction capacitance 29 3.2 Rate of convergence of two spheres formula for lOnm radius spheres 40 3.3 Capacitance approximations for 20nm radius aluminium hemispheres 41 PUBLICATIONS Aspects of this work have been published as : J.R. Barker, S. Roy, and S. Babikir, Trajectory Representations, Fluctuations, and Stability of Granular Electronic Devices. In 'Science and Technology of Mesoscopic Structures' in Japan, edited by S. Namba, C. Hamaguchi, and T. Ando, Springer-Verlag: London, Tokyo, New York, 213-232, (1992). J.R. Barker, J.M.R. Weaver, S. Babikir, and S. Roy, Theory, Modelling and Construction of Single-Electronic Systems. In 'Second International Symposium on New Phenomena in Mesoscopic Structures' in Hawaii, (1992). S. Roy, J.R. Barker, and A. Asenov, System Simulation Tools for Single- Electronic Devices. In 'Proceedings of the International Workshop on Computational Electronics' in Leeds, England, edited by C.M.Snowden and M.J. Howes, (1993). J.R. Barker, S. Babikir, and S. Roy, Single Electron Transport in Nanostructure Systems. Submitted to Physica B Publications associated with this research include : S. Roy, A. Asenov, and J. R. Barker, Optimum Partitioning of Topologically Rectangular Grids. Accepted for 'International EUROSIM Conference HPSN Challenges in Telecomp and Telecom: Parallel Simulation of Complex Systems and Large-Scale Applications' in Delft, Netherlands, (1996) S. Roy, A. Asenov, A.R. Brown and J. R. Barker, Partitioning of Topologically Rectangular Finite Element Grids. Accepted for '4th ACME Conference on Computational Mechanics in the UK' in Glasgow, Scotland, (1996) A. Asenov, A.R. Brown, S. Roy and J. R. Barker, Topologically rectangular grids in the parallel simulation of semiconductor devices. In 'International Workshop on Computational Electronics' in Tempe, Arizona, (1995) (Will appear in as regular paper in VLSI Design) Publications (cont.) A.R. Brown, A. Asenov, S. Roy and J. R. Barker, Parallel 3D Finite Element Power Semiconductor Device Simulator based on topological rectangular grid. In 'Simulation of Semiconductor Devices and Processes' vol 6, edited by H. Ryssel, P.Pichler, Springer-Verlag Wien, New York, p.336-339, (1995) A.R. Brown, A. Asenov, S. Roy and J. R. Barker, Development of a parallel 3D finite element power semiconductor device. IEE Digest, 1995/064, 2, 1-6 (1995) CHAPTER 1 INTRODUCTION Since the invention of the transistor in 1947 and its subsequent service in integrated circuits, the history of digital electronics has been a relentless quest for device minia- turisation. Three facts drive this search. Firstly, miniaturisation reduces the volumes across which electric fields act, allowing lower power dissipation. Secondly, lower capacitance and shorter interconnects lead to faster systems. Finally, miniaturisation (in tandem with increased chip size) allows more devices on a chip and thus reduces relative costs [1]. It is obvious that the feature size of modern devices cannot be reduced without limit. Eventually it will rival the electron wavelength. In this regime many classical con- cepts become invalid. A more detailed quantum mechanical approach is needed to fully understand electron transport, and develop the new concepts necessary to de- scribe device operation. There is also the opportunity to exploit quantum mechanics and develop novel de- vices. Apart from any intrinsic benefits gained from quantum mechanical operation, such devices will retain the power, speed, and cost benefits which miniaturisation brings. In recent years, new developments in both theory and experiment [2] have allowed the serious consideration of an electronics technology based on one basic quantum mechanical phenomena - the discrete nature of electron tunnelling through a potential barrier. Such granular electronic devices include those constructed from ultrasmall normal tunnelling junctions. They exhibit charging effects including the Coulomb blockade and correlated electron tunnelling. These devices allow operation at the limit of one transferred carrier per bit, the information theoretic limit. As such, they are often referred to as single electronic devices. 1.1 Properties of Single Electronic Systems Two properties of tunnelling junction systems are vital to the operation of single electronic devices. Firstly, ultrasmall junctions allow ultrasmall junction capacitance. The electrostatic charging energy of a single tunnelling event across such a junction is,