Lecture 21 Analog-to-Digital Converters (continued) –Residue Type ADCs • Two-Step flash • Pipelined ADCs – Concept and basics of the architecture – Effect of building block non-idealities on overall ADC performance • Sub-ADC • Sub-DAC • Gain stage – Error correction by adding redundancy – Digital calibration – Correction for inter-stage gain nonlinearity EECS 247 Lecture 21: Data Converters: Nyquist Rate ADCs © 2010 Page 1 ADC Architectures • Slope type converters • Successive approximation • Flash • Interpolating & Folding • Residue type ADCs – Two-step Flash – Pipelined ADCs – … • Time-interleaved / parallel converter • Oversampled ADCs EECS 247 Lecture 21: Data Converters-Nyquist Rate ADCs © 2010 Page 2 Two-Step Example: (2+2)Bits 11 V in 2-bit ADC 2-bit ADC Dtuo0110 V in 00 0 1 2 3 ??? ]B S0.5 L + [ eq1-0.5 D = V+ e out in q1 0 1 2 3 ADC Input [LSB] • Using only one ADC: output contains large quantization error • "Missing voltage" or "residue" ( -e ) q1 • Idea: Use second ADC to quantize and add -e q1 EECS 247-Lecture 21 Residue Type ADCs © 2010 Page 3 Two Stage Example Vref1 Vref2 -e V q1 in “Coarse“ - + “Fine“ 2-bit ADC 2-bit DAC 2-bit ADC -e +e q1 q2 + D = V + e -e +e out in q1 q1 q2 • Use DAC to compute missing voltage • Add quantized representation of missing voltage • Why does this help? How about e ? q2 • Since maximum voltage at input of the 2ndADC is V /4 then for 2ndADC ref1 V =V /4 and thus e = e /4 =V /16 4bit overall resolution ref2 ref1 q2 q1 ref1 EECS 247-Lecture 21 Residue Type ADCs © 2010 Page 4 Two Step (2+2) Flash ADC 4-bit Straight Flash ADC Ideal 2-step Flash ADC V V V in in in Voltage quantized by 2ndADC EECS 247-Lecture 21 Residue Type ADCs © 2010 Page 5 Two Stage Example -e q1 11 V /22 10 V Second ADC ref1 V V 01 ref2 “Fine“ ref1 in 00 00 01 10 11 First ADC “Coarse“ • Fine ADC is re-used 22times • Fine ADC's full scale range needs to span only 1 LSB of coarse quantizer V V e  ref2  ref1 q2 22 2222 EECS 247-Lecture 21 Residue Type ADCs © 2010 Page 6 Two-Stage (2+2) ADC Transfer Function D out 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 V in V ref1 Coarse Fine Bits Bits (MSB) (LSB) EECS 247-Lecture 21 Residue Type ADCs © 2010 Page 7 Residue or Multi-Step Type ADC Issues re Vin Coarse ADC DAC Fine ADC nibmo )2BtiB- (B1-Bit) (B1-Bit) Residue ((oBp2ti-oBniat)l) C tiB +1B ( • Operation: – Coarse ADC determines MSBs – DAC converts the coarse ADC output to analog-Residue is found by subtracting (V -V ) in DAC – Fine ADC converts the residue and determines the LSBs – Bits are combined in digital domain • Issue: 1.Fine ADC has to have FS=FS /2B1 & precision in the order of overall ADC coarse 1/2LSB 2.Speed penalty Need at least 1 clock cycle per extra series stage to resolve one sample EECS 247-Lecture 21 Residue Type ADCs © 2010 Page 8 Solution to Issue (1) Reducing Precision Required for Fine ADC 2-bit ADC 2-bit DAC G=2B1 2-bit ADC -e V q1 in “Coarse“ - + “Fine“ -e +e q1 q2 + D = V + e -e +e out in q1 q1 q2 • Accuracy needed for fine ADC relaxed by introducing inter-stage gain – Example: By adding gain of x(G=2B1=4) prior to fine ADC in (2+2)bit case, precision required for fine ADC is reduced to 2-bit only! – Additional advantage-coarse and fine ADC can be identical stages EECS 247-Lecture 21 Residue Type ADCs © 2010 Page 9 Solution to Issue (2) Increasing ADC Throughput T/H+(G=2B1) 2-bit ADC 2-bit DAC -e V q1 in “Coarse“ - + “Fine“ T/H 2-bit ADC + D = V + e -e +e out in q1 q1 q2 • Conversion time significantly decreased by employing T/H between stages – All stages busy at all times operation concurrent – During one clock cycle coarse & fine ADCs operate concurrently: • First stage samples/converts/generates residue of input signal sample # n • While 2ndstage samples/converts residue associated with sample # n-1 EECS 247-Lecture 21 Residue Type ADCs © 2010 Page 10 Residue Type ADCs • Two-Step flash • Pipelined ADCs – Basic operation – Effect of sub-ADC, sub-DAC, gain stage non-idealities on overall ADC performance • Error correction by adding redundancy • Digital calibration • Correction for inter-stage gain nonlinearity – Implementation • Practical circuits • Stage scaling • Combining the bits • Stage implementation –Circuits –Noise budgeting • How many bits per stage? EECS 247-Lecture 21 Pipelined ADCs © 2010 Page 11 Pipeline ADC Block Diagram V V Stage 1 res1 Stage 2 res2 Stage k V in B Bits B Bits B Bits 1 2 k MSB... ...LSB Align and Combine Data Digital output (B + B + ... + B) Bits 1 2 k • Idea: Cascade several low resolution stages to obtain high overall resolution (e.g. 10bit ADC can be built with series of 10 ADCs each 1-bit only!) • Each stage performs coarse A/D conversion and computes its quantization error, or "residue“ • All stages operate concurrently EECS 247-Lecture 21 Pipelined ADCs © 2010 Page 12 Pipeline ADC Concurrent Stage Operation f acquire convert ... 1 f convert acquire ... 2 Stage 1 Stage 2 Stage k V in B Bits B Bits B Bits 1 2 k f 1 CLK f Align and Combine Data 2 Digital output (B + B + ... + B)Bits 1 2 k • Stages operate on the input signal like a shift register • New output data every clock cycle, but each stage introduces at least ½ clock cycle latency EECS 247-Lecture 21 Pipelined ADCs © 2010 Page 13 Pipeline ADC Latency Note: One conversion per clock cycle & 8 clock cycle latency [Analog Devices, AD 9226 12bit ADC Data Sheet] EECS 247-Lecture 21 Pipelined ADCs © 2010 Page 14 Pipelined ADC Characteristics • Number of components (stages) grows linearly with resolution • Pipelining – Trading latency for overall component count – Latency may be an issue in e.g. control systems – Throughput limited by speed of one stage Fast • Versatile: 8...16bits, 1...400MS/s • One important feature of pipelined ADCs: many analog circuit non-idealities can be corrected digitally EECS 247-Lecture 21 Pipelined ADCs © 2010 Page 15 Pipeline ADC Digital Data Alignment f acquire convert ... 1 f convert acquire ... 2 Stage 1 Stage 2 Stage k V in B Bits B Bits B Bits 1 2 k f 1 CLK f2 + + Dout CLK CLK CLK • Digital shift register aligns sub-conversion results in time EECS 247-Lecture 21 Pipelined ADCs © 2010 Page 16 Cascading More Stages Vref Vref /2B1 Vref /2(B1+B2) Vref /2(B1+B2+B3) V in B bits B bits B bits ADC 1 2 3 ADC DAC + - • LSB of last stage becomes very small • All stages need to have full precision • Impractical to generate several V ref EECS 247-Lecture 21 Pipelined ADCs © 2010 Page 17 Pipeline ADC Inter-Stage Gain Elements V V V V ref ref ref ref T/H&2B1 T/H&2B2 T/H&2B3 V in B bits B bits B bits ADC 1 2 3 ADC DAC + - • Practical pipelines by adding inter-stage gain use single V ref • Precision requirements decrease down the pipe – Advantageous for noise, matching (later), power dissipation • All stages can operate concurrently Throughput 1sample/clock cycle EECS 247-Lecture 21 Pipelined ADCs © 2010 Page 18 Complete Pipeline Stage -e -G V q1 V in + res - B-bit B-bit ADC DAC D V ref “Residue Plot“ V res E.g.: B=2 G=22=4 0 Note: None of the blocks have ideal performance 0 V Vref in Question: What is the effect of the non-idealities? EECS 247-Lecture 21 Pipelined ADCs © 2010 Page 19 Pipeline ADC Errors • Non-idealities associated with sub-ADCs, sub-DACs and gain stages  error in overall pipeline ADC performance • Need to find means to tolerate/correct errors • Important sources of error – Sub-ADC errors-comparator offset – Gain stage offset – Gain stage gain error – Sub-DAC error EECS 247-Lecture 21 Pipelined ADCs © 2010 Page 20