Process and Device Simulation for MOS-VLSI Circuits NATO ASI Series Advanced Science Institutes Series A Series presenting the results of activities sponsored by the NATO Science Committee, which aims at the dissemination of advanced scientific and technological knowledge, with a view to strengthening links between scientific communities. The Series IS published by an International board of publishers in conjunction with the NATO Scientific Affairs Division A Life Sciences Plenum Publishing Corporation B Physics London and New York C Mathematical and D. Reidel Publishing Company Physical Sciences Dordrecht and Boston D Behavioural and Martinus Nijhoff Publishers Social Sciences BostonlThe HagueiDordrecht/Lancaster E Applied Sciences F Computer and Springer-Verlag Systems Sciences Heidelberg/Berlin/New York G Ecological Sciences Series E: Applied Sciences - No. 62 Process and Device Simulation for MOS-VLSI Circuits edited by Paolo Antognetti University of Genova Genova, Italy Dimitri A. Antoniadis Massachusetts Institute of Technology Cambridge, MA, USA Robert W. Dutton Stanford University Stanford, CA, USA William G. Oldham University of California Berkeley, CA, USA 1983 Martinus Nijhoff Publishers .... A member of the Kluwer Academic Publishers Group •• Boston I Tile Hague I Dordrecht I Lancaster .~ Published In cooperation with NATO SClenllflc Affairs DIvIsion Proceedings of the NATO Advanced Study Institute on Process and Device Simulation for MOS-VLSI Circuits, SOGESTA, Urbina, Italy, July 12 - 23, 1982 Library of Congress Cataloging in Publication Data NATO /,dvanced Study Insti tute on Process and Devi ce Simulation for MOS-VLSI Circuits (1982 : ';rbino, Italy) Process and device simulation for MOS-VLSI circuits. (NATO ASI series. Series F., Applied sciences ; no. 62) "Proceedings of the NATO Advanced' Study Institute on Process and Device Simulation for MOS-VLSI Circuits, SOGESTA Urbino, Italy, July 12-23, 1982"--T.p. verso. "pubiished in cooperation wi th NATO Scientific Af- fairs Divi.sjon." 1. Integrated circuits--Very large scale in~egration --Simulation melhods--Congresses. 2. Metal oxide semi- conductors--Simulation methods--Congresses. I. Antognetti, Paolo. II. Title. III. Series: NATO advanced science institutes series. Series E, Applied sciences ; no. 62. TK7874.N343 1982 621.381'73 83-4018 ISBN-13: 978-94-009-6844-8 e-ISBN-13: 978-94-009-6842-4 001: 10.1007/978-94-009-6842-4 Distributors for the United States and Canada: Kluwer Boston, Inc., 190 Old Derby Street, Hingham, MA 02043, USA Distributors for all other countries: Kluwer Academic Publishers Group, Distribution Center, P.O. Box 322, 3300 AH Dordrecht, The Netherlands All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, mechanical, photocopying, rec'Jrding, or otherwise, without the prior written permission of the publishers, Martinus Nijhoff Publishers, P.D. Box 566, 2501 CN The Hague, The Netherlands Copyright © 1983 by Martinus Nijhoff Publishers, The Hague Softcover reprint of the hardcover 1s t edition 1983 LIST OF LECTURERS ~~'f. P. Antognettf Prof. W. G. Oldham Mr. Ginetto Addiego !stituto di Elettrotecnica University of Cal ifornia Univ. of California. Berkeley V.le Causa. 13 EECS Dept. - Cory Hall Dep. of EECS. ERI.. 16145 GENOVA BERKELEY CA. 94720 Roan 332 Cory Hall ill.!:.! U.S.A. BERKELEY. CALIFORNIA 94720 ~ Prof. D.A. Antonfadis Prof: J. P1 ummer MIT - EECS Dept. Stanford University Dr. Giuseppe Barouscia Room 13 - 3014 Stanford Electronics Labs. SGS CAMBRIDGE MA. 02139 STANFORD CA. 94305 Central R (, 0 !!.:.U:. U.S.A. Vi a 01 ivetti. 2 AGRATE BRIANZA (MI) ITALY Prof. C. Claeys Dr. H. Ryssel Kathol feke Universiteit Leuven Fraunhofer Institut !FT Departement Elektrotechniek Paul Gerhardt Allee 42 Dr. J.J.J. Bastiaens Kard. Mercier1aan 94 8000 MUNCHEN 60 Philips Research Labs 3030 HEVERLEE WEST GERMANY Prof. Holstlaan WAG 1-3-13 ~ EINDHOVEN THE NETHERLANDS Dr. K. Salsburg Prof. R. W. Dutton I.B.M. Stanford University 9500 God wi n Dr. Dr. Walter Bella Stanford Electronics Labs. MANASSAS. VA. 22110 C. 5. E. L. T. STANFORD CA. 94305 U.S.A. Via G. Reiss Romoli 274 .!L:i:.8.:. 10148 TORINO ITALY Prof. S. Selberherr Prof. J. Gibbons Technische Universitat Wien Stanford University Gusshausstrasse 27-29 Ing. Delfreo Bianchi Stanford Electronics Labs. A-1040 WIEN OLIVETTI - DIDAU/QST STANFORD CA. 94305 .B!lllill Scanna9no A U.S.A. IVREA (TO) ITALY Prof. T. Sigmon Prof. C. R. Helms Stanfords University Stanford University Stanford Electronics Labs. Prof. Giacomo Bisio Stanford Electronics Labs. STANFORD CA. 94305 Istituto di Elettrotecnica STANFORD CA. 94305 V.le Causa. 13 ~ .!L:i:.8.:. 16145 GENOVA illhl Dr. R. Tielert Dr. L. Mef SIEMENS ZFE ME 212 Fa i rch f1 d Postfach 830952 Dr. B. Broich 4001 Miranda Ave. 8000 MUNCHEN 83 BBC Brown. Boveri (, Co .• Ltd. PALO ALTO CA. 94304 WEST GERMANY Research Center U.S.A. CH-5405 BADEN SWITZERLAND Mr. Stan Abbe100s Prof. A. Neureuther Bell Telephone MFG CO. University of California Gasmeterlaan 106 Ing. Antonio Buonomo EECS Dept. - Cory Hall 9000 GENT Universit~ della Calabria BERKELEY CA. 94720 Dip. Elettrico !M!!:!t! U.S.A. ARCAVACATA RENDE (CS) ITALY VI Dr. Alan Butler Prof. Gianni Conte Mr. A.G.R. Evans Plessey Research (Caswell) Ltd., Ist. Elettronica e Telec. Po- Dept. of Electronics Allen Clark Research Centre litecnico Southampton University Caswell Towcester C.so Duca degli Abruzzi, 24 SOUTHAMPTON NORTHANTS TORINO ~ ENGLAND !TAl. Y Mr. Pau 1 Fahey Mr. Alistair Buttar Mr. Christopher Davi s Stanford University E1 ectrica 1 Eng. Deot. RCA Solid State, MZ 177 Stanford Electronics Lab. Edinburgh University U.S. Rte 202 AEL 231 Mayfield Rd. - EDINBURGH SOMERVILLE NJ 08876 STANFORD, CA 94305 SCOTLAND U.S.A. U.S.A. Mr. E.R. Campbell Mrs. Kristin M. De t~eyer Mr. John Faricell i British Aerospace K.U.L. - ESAT. 91 DEP. ELEKTR. 325 Phillips Hall P.B. 299 Karelinaal Mercierlaan 9<t Cornell Un ivers i ty SITE A B-3030 HEVERLEE ITHACA, NY 14853 STEVENAGE BELGIUM ~ ENGLAND Ing. Giovanni De Micheli Ing. C. Fasce Mr. Caquot Via Traiano 13 SGS - Central R&D CNET I-20149 MILANO Via Olivetti, 2 B.P. 42 ITALY AGRATE BRIANZA (MI) F 38240 MEYLAN ITALY ~ Dr. Yves Depeursinge LSRH Mr. Gerard Ghibaudo Ing. Daniele Caviglia Rue Breguet 2 ENSER, ERA CNRS 659 Istituto di Elettrotecnica 2000 NEUCHATEL 23 Avenue des Martyrs V.le Causa, 13 SWITZERLAND 38031 GRENOBLE CEDEX GENOVA FRANCE ill!:l Ing. Ennanno Di Zitti Istituto di Elettrotecnica Dr. A.E. Glaccum Mr. Peter Claus V.le Causa, 13 British Telecom Research Labs. Inst. fUr Hochfrequenztechnik 16145 GENOVA Martlesham Heath, Ipswich, Techn. Hochschule Darmstadt ITALY IP57RE Merckstr. 25 ENGLAND 0-6100 DARMSTADT WEST GERMANY Mr. K. Doganis ICL AEL 231 Mr. Richard J. Gledhill Stanford University Middlesex Polytechnic Bill Cochran STANFORD CA 94305 Bounds Green Road Bell Labs ~ LONDON N11 2NQ 555 Union Blvd. §..8.illlli ALLENTOWN PA. 18018 .!!.:..U.:. Dr. J.D. Eades Robert Gordon's Inst. of Mr. James A. Greenfield TeChnology AEL 127 A Mr. Collard School hill Stanford University l.S.E.N. ABERDEEN AB9 1FR STANFORD, CA 94305 3, rue F. Baes SCOTLAND U.K. U.S.A. 59046 LlLLE CEDEX ~ VII Mr. S.E. Hansen Mr. Hon Bor Lo Mr. Rob Moolenbeek Stanford University Dept. of Electrical Eng. 181 Claybrook Rd, AEL Bl dg. RoOOl 229 University of Hong Kong DOVER MASS 02030 STANFORD, CAL. 94305 Pokfulam Road ~ U.S.A. HONG KONG Mr. Sharad N. Nandgaonkar Mr. Jan Haraldsen Ing. Claudio LOOIbardi Univ. of California, Berkeley Okrivn. 27 SGS Oep. of EECS, ERL 1349 RYKKINN Central R&D RoOOl 332 Cory Hall NORWAY Via 01 ivetti, 2 BERKELEY, CALIFORNIA 94720 U.S.A. AGRANTE BRIANZA (MI) Mr. H.B. Harrison ~'r. Istvan Madas Mr. Theo Naten Royal Melbourne Inst. of SIEMENS AG Bell Telephone MFG CO. Tech. Ltd. (RMIT) Mch B - WIS TE CAD 12 Gasmeterlaan 106 Balanstr. 73 9000 GHENT 0-8000 r~UNCHEN 80 BELGIUM 124, La Trobe St., GERMANY MELBOURNE 3000 AUSTRALIA Mr. I sma il Okter Mr. L. r,'ader Istanbul Tech. Univ., Electrical SIEMENS, ME 31 Facul ty Mr. Max Hodeau Postfach 830952 ITU Elektrik Fakultesi I.B.M. France - Service 1768 0-8000 MUNCHEN 83 Elektronik ve Yuksek Frekans 224, Bd. J. Kennedy WEST GERMANY Teknigi Kursusu 91102 CORBEIL-ESSONNES GUMUSSUYU - ISTANBUL FRANCE TURKEY Mr. Ilmer;co Marrocco I.N.R.I.A. Mr. I. John Rocquencourt BP 105 Mr. Payo-Casares P.B. 252 78 153 LE CHESNAY Thomson-EFCIS D.T. Six Hill sWay FRANCE Av. des Martyrs - B.P. 217 B.A.e. 38019 GRENOBLE CEDEX STEVENAGE HERTS ~ UN ITED KI NGDOM P~of. Guido Masetti UniversiU di Ancona Via Montagnola, 30 Or.ssa Luisa Polignano 60100 ANCONA SGS - Central R&D Mr. Michael Roy Kump ITALY Vi a 01 i vett i, 2 Stanford Universi ty AGRATE BRIANZA (MI) AEL 231B ITALY STANFORD, CALIFORNIA 94305 U.S.A. Mr. Hugh Mc Neillie General Instrument Newark road Mr. Ma rk Readdi e EASFIELD INDUSTRIAL EST G.E.C. Hirst Research Centre Mr. Ala n Lewi s GLEN ROTHES FIFE Eas t Lane, Wemb J ey G.E.C. Hirst Research Centre SCOTLAND MIDDLESEX RoOOl B 18 ENGLANO East Lane, Wembley MIDDLESEX UNITED KINGDOM Mrs. M. Teresa Mendes Univers;dade de Coimbra Mr. P.M. Savjani Dept. Electrotecnia Rutherford Appel ton Laboratory F.C.T.U.C. CHILTON, OIOCOT OXON 3000 COIMBRA ~ PORTUGAL VIII Mr. Claude Schlesser Mr. A. Stolmeijer Dr. A.J. Walton Bell Telephone MFG CO. Twente University of Technology Electr1cal Eng. Dept. Microelectronics Lab. Dep. of Electrical Eng. Univ. of Edi nburgh 106, Gasmeterlaan P.O. Box 217 Kings Buildings 9000 GENT 7500 AE ENSCHEDE ED INBURGH EHG 3JL THE NETHERLANDS SCOTLAND ~ Mr. Yosi J. Shacham Diamand Mr. Bernard Tremintim Mr. Per Wehlin Mi core 1e ctron i c Research Center, Matra Harris Semiconducteur Royal lnst. of Technology, Stockholm Solid State Institute, Techion BP 942 - La Chantrerie Inst. f. Tillampad elektronik Technion City. 44075 NANTES CEDEX 5-10044 STOCKHOLM HAIFA FRANCE MIDi ~ Mr. Hans Paul Tuinhout Dr. -Christoph Weigel Dr. Martine Simard-Nonnandin Phil ips Research Laboratory Wacker Chemitronic Northern Telecom Limited WAG-1-4-18 Postfach 1140 P.O. Box 3511 - Station C EINDHOVEN 0-8263 BURGHAUSEN OTTAWA ONTARIO KIY 4H7 THE NETHERLANDS WEST GE RMANY ~ Ing. Massimo Vanzi Dr. Claudine Simson SGS No rthern Telecom Limi ted Central R&D P.O. Box 3511, Station C, Vi a 01 ivetti, 2 Dept. P 881 AGRATE BRIANZA (MI) OTTAWA, ONTARIO KIY 4H7 illhr CANADA IX TABLE OF CONTENTS Page PREFACE X LIST Of LECTURER~ V DIFFUSION IN SiLICON by Dimitri A. Antoniadis 1 THERMAL OXIDATION: KINETICS, CHARGES, PflYSICAL MODELS, AND INTER- ACTION WITH OTHER PROCESSES IN VLSI DEVICES by James D. Plummer and Bruce E. Deal 40 THE USE OF CHLORINATED OXIDES AND INTRINSIC GETTERING TECHNIQUES FOR VLSI PROCESSING by C. L. Claeys 08 ION IMPLANTATION by Heiner Ryssel and Klaus Hoffman 125 BEAM ANNEALING OF ION IMPLANTED SILICON by James F. Gibbons 180 MATERIALS CHARACTERIZATION by C. R. Helms 210 MODELING OF POLYCRYSTALLINE SILICON STRUCTURES FOR INTEGRATED CIRCUIT FABRICATION PROCESSES by Len Mei, Robert W. Dutton and Stephen E. Hansen 264 TWO-DIMENSIONAL PROCESS SIMULATION - SUPRA by Michael Kump and Robert W. Dutton 304 NUMERICAL SIMULATION OF IMPURITY REDISTRIBUTION NEAR MASK EDGES by R. Tielert 343 OPTICAL AND DEEP UV LITHOGRAPHY by W. G. Oldham 397 WAFER TOPOGRAPHY SIMULATION by A. R. Neureuther 411 ANALYSES OF NONPLANAR DEVICES by James A. Greenfield, Graig H. Price and Robert W. Dutton 432 TWO DIMENSIONAL MOS-TRANSISTOR MODELING by S. Selberherr, A. Schutz and H. Potzl 490 FIELDAY - FINITE ELEMENT DEVICE ANALYSES by K. A. Salsburg 502 x PREFACE P. Antognetti University of Genova, Italy Director of the NATO ASI The key importance of VLSI circuits is shown by the national efforts in this field taking place in several countries at differ- ent levels (government agencies, private industries, defense de- partments). As a result of the evolution of IC technology over the past two decades, component complexi ty has increased from one single to over 400,000 transistor functions per chip. Low cost of such single chip systems is only possible by reducing design cost per function and avoiding cost penalties for design errors. Therefore, computer simulation tools, at all levels of the design process, have become an absolute necessity and a cornerstone in the VLSI era, particularly as experimental investigations are very time-consuming, often too expensive and sometimes not at all feasible. As minimum device dimensions shrink, the need to understand the fabrication process in a quanti tati ve way becomes critical. Fine patterns, thin oxide layers, polycristalline silicon interco~ nections, shallow junctions and threshold implants, each become more sensitive to process variations. Each of these technologies changes toward finer structures requires increased understanding of the process physics. In addition, the tighter requirements for process control make it imperative that sensitivities be unde~ stood and that optimation be used to minimize the effect of sta- tistical fluctuations. Over the past years, models have been developed which make it possible to simulate IC fabrication process physics. Moreover,