EELLEENN 668899--660033 PPiippeelliinnee AADDCC’’ss FFeebbrruuaarryy 22000000 Content • Interest of pipeline ADCs • The Origins of Pipeline ADCs • Basic Architecture • Digital Correction • Detailed example • Performance evaluation • Design-performance relations Interest of the Pipeline ADCs • A Figure-of-merit to evaluate the performance of an ADC is its information transfer capacity: ITC=2NCS where ITC is the Information Transfer Capacity in symbols/sec, N is the number of bits and CS is the Conversion Speed, • For example, an 8-bit, 1GSPS ADC has an ITC of 2.56e11, whereas a 20-bit 44.1KSPS ADC has an ITC of 4.62e10, • The state of the art in ADCs is presently given by a 14-bit, 80MSPS pipeline ADC, which provides an ITC of 1.3e12 symbols/sec. Some Products and Performance Ref / Year Feature Technology Results Area (mm2) Power/Voltage JSSC 12/1999 Pipelined delta- 1.2u CMOS SNR74dB 48 324mW/3.3v sigma 18Msps JSSC 12/1997 Pipelined delta- 0.6u CMOS 16 bits 35 550Mw/5v sigma 20Msps JSSC 12/1998 Self calibrating 0.5u CMOS 12bits 10Msps 15 335mW/3.3v JSSC 12/1996 Microcontroller 1u BiCMOS 16bits 1Msps 35 200mW/5v calibrating ISSCC98 Analog 1.0u CMOS 10 bits 47 650mW/5v calibrating 40Msps ISSCC98 2 channels 0.5u CMOS 8bits 75Msps 5.5 70mW/3.3v ISSCC98 2 channels 1u CMOS 10bits,40Msps 42 565mW/5v ISCAS98 Current mode 0.5u CMOS 8 bits 20Msps N/A 22mW/2.4v CAS II99 Good linearity 0.5u CMOS 12 bits3.3Msps N/A 300mW/5v Device Resolution Conv. Supply(v) SNR(dB) Power(mW) Rate(Msps) Texas Instruments Products THS1206 pipeline 12 6 2.7-5.5 N/A 210 TLV5580 pipeline 8 80 3.3 46 165 TLC5540 semiflash 8 40 5 45 85 Analog Devices Products AD9202 pipeline 10 32 3 N/A 90 AD9203 pipeline 10 40 3 N/A 50 MAXIM Products MAX1201 14 2.2 5 83 269 The Origins of Pipeline ADCs 1- The Flash ADC Vref Vin • Each comparator has its own 2n-1 threshold voltage, spaced by Comparators 1 LSB, • The input is fed to all the Digital Output comparators in parallel, • The output of the Encoder comparators is in “thermometer” format, • An encoder is used to convert to binary format. 2- Sub-Ranging ADCs • The input is first converted MSB 3 Bit A/D by a simple 3-bits flash ADC, V in Converter • The digital value is converted back in analog format by a 3-bit DAC and subtracted from the input, D/A Coverter this gives a residue, • The residue is multiplied to Gain get the full range, and then converted by a second flash. Sign 3 Bit A/D Converter LSB More on Sub-Ranging First Stage Second Stage Very High Speed l 1 Conversion/Clock l 1/2 Clock Latency l Higher Resolution with Less l Hardware: 2 X 3bit = 14 Comp. 6bit = 63 Comp. Lower Power Dissipation l Smaller Input Capacitance l Can be Interleaved l Requires High Precision Interstage l 3bits + 3bits Processing Hardware Still Increases Exponentially l within Each Flash 3- The Pipeline ADC Basic Architecture f f f f Analog Analog Analog Analog Vin Stage Stage Stage Stage MSB LSB The principle of sub-ranging ADC can be pushed to the limit of having only one bit per stage, At this point, each flash ADC is nothing more than a simple comparator, Also, the data is transferred in a pipeline fashion: when the data is sent to the second stage, another sampled data is fed to the first stage, The result is a latency delay equal to the number of stages. Basic Block Architecture Implemented by a single programmable amplifier + X2 Analog input Residue - (from previous (to next stage) stage) 21 bit A/D 12 bit D/A (Comparators) Digital Out The analog stage is formed of a 2 bits flash ADC, a 2 bits DAC and a adder/gain stage. The output is called the residue and is sent to the next stage. Functionality of the Basic Block Residue Clock + In X2 Residue - 1 bit A/D 1 bit D/A In 1 Digital Out = - + - > Stage(n) 2(Stage(n 1) V ) if Stage(n 1) V ref mid = - - - > Stage(n) 2(Stage(n 1) V ) if Stage(n 1) V ref mid