PCI Express™® Card Electromechanical Specification Revision 1.1 2.0 March 28, 2005 April 11, 2007 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.12.0 Revision Revision History Date 1.0 Initial release. 7/22/2002 1.0a Incorporated WG Errata C1-C7 and E1. 4/15/2003 1.1 Incorporated approved Errata and ECNs. 03/28/2005 2.0 Added support for 5 GT/s data rate. 4/11/2007 PCI-SIG® disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of the specification. Questions regarding this specification or membership in PCI-SIG may be forwarded to: Membership Services www.pcisig.com E-mail: [email protected] Phone: 503-291-2569 619-0569 Fax: 503-297-1090644-6708 Technical Support [email protected] DISCLAIMER This PCI Express Card Electromechanical Specification is provided “as is” with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI, PCI Express is a trademark, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or service marks of their respective owners. Copyright © 2002-20052007 PCI-SIG 2 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.12.0 Contents 1. INTRODUCTION....................................................................................................................9 1.1. TERMS AND DEFINITIONS.....................................................................................................9 1.2. REFERENCE DOCUMENTS...................................................................................................10 1.3. SPECIFICATION CONTENTS.................................................................................................11 1.4. OBJECTIVES.............................................................................................................................11 1.5. ELECTRICAL OVERVIEW.....................................................................................................12 1.6. MECHANICAL OVERVIEW...................................................................................................13 2. AUXILIARY SIGNALS........................................................................................................15 2.1. REFERENCE CLOCK...............................................................................................................16 2.1.1. Low Voltage Swing, Differential Clocks....................................................................16 2.1.2. Spread Spectrum Clocking (SSC)...............................................................................17 2.1.3. REFCLK AC Specifications........................................................................................18 2.1.4. REFCLK Phase Jitter Specification For 2.5 GT/s Signaling Support.......................21 2.1.5. REFCLK Phase Jitter Specification For 5 GT/s Signaling Support..........................22 2.2. PERST# SIGNAL......................................................................................................................22 2.2.1. Initial Power-Up (G3 to S0).......................................................................................23 2.2.2. Power Management States (S0 to S3/S4 to S0)..........................................................25 2.2.3. Power Down...............................................................................................................27 2.3. WAKE# SIGNAL......................................................................................................................29 2.4. SMBUS (OPTIONAL)...............................................................................................................32 2.4.1. Capacitive Load of High-power SMBus Lines...........................................................32 2.4.2. Minimum Current Sinking Requirements for SMBus Devices....................................33 2.4.3. SMBus “Back Powering” Considerations.................................................................33 2.4.4. Power-on Reset..........................................................................................................33 2.5. JTAG PINS (OPTIONAL).........................................................................................................34 2.6. AUXILIARY SIGNAL PARAMETRIC SPECIFICATIONS...................................................35 2.6.1. DC Specifications.......................................................................................................35 2.6.2. AC Specifications.......................................................................................................36 3. HOT INSERTION AND REMOVAL..................................................................................37 3.1. SCOPE 37 3.2. PRESENCE DETECT................................................................................................................37 4. ELECTRICAL REQUIREMENTS.....................................................................................39 4.1. POWER SUPPLY REQUIREMENTS......................................................................................39 4.2. POWER CONSUMPTION........................................................................................................40 4.3. POWER SUPPLY SEQUENCING............................................................................................41 4.4. POWER SUPPLY DECOUPLING............................................................................................42 4.5. ELECTRICAL TOPOLOGIES AND LINK DEFINITIONS....................................................42 4.5.1. Topologies..................................................................................................................42 4.5.2. Link Definition............................................................................................................44 4.6. ELECTRICAL BUDGETS........................................................................................................45 4.6.1. AC Coupling Capacitors............................................................................................46 4.6.2. Insertion Loss Values (Voltage Transfer Function)...................................................46 4.6.3. Jitter Values................................................................................................................48 4.6.4. Crosstalk.....................................................................................................................50 3 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.12.0 4.6.5. Lane-to-Lane Skew.....................................................................................................51 4.6.6. Equalization...............................................................................................................51 4.6.7. Skew within the Differential Pair...............................................................................51 4.6.8. Differential Data Trace Impedance...........................................................................52 4.6.9. Differential Data Trace Propagation Delay..............................................................52 4.7. EYE DIAGRAMS AT THE ADD-IN CARD INTERFACE.....................................................53 4.7.1. Add-in Card Transmitter Path Compliance Eye Diagram at 2.5 GT/s......................53 Add-in Card Transmitter Path ..................................................................................54 4.7.2. Compliance Eye Diagrams at 5 GT/s.........................................................................54 4.7.3. Add-in Card Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s.............57 4.7.4. Add-in Card Minimum Receiver Path Sensitivity Requirements at 5 GT/s................59 4.7.5. System Board Transmitter Path Compliance Eye Diagram at 2.5 GT/s....................60 4.7.6. System Board Transmitter Path Compliance Eye Diagram at 5 GT/s.......................61 4.7.7. System Board Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s...........65 4.7.8. System Board Minimum Receiver Path Sensitivity Requirements at 5 GT/s..............66 5. CONNECTOR SPECIFICATION.......................................................................................69 5.1. CONNECTOR PINOUT............................................................................................................69 5.2. CONNECTOR INTERFACE DEFINITIONS...........................................................................73 5.3. SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES................................81 5.3.1. Signal Integrity Requirements....................................................................................81 5.3.2. Signal Integrity Requirements and Test Procedures for 2.5 GT/s Support...............81 5.3.3. Signal Integrity Requirements and Test Procedures for 5 GT/s Support...................84 5.3.3.1 Test Fixture Requirements......................................................................86 5.4. CONNECTOR ENVIRONMENTAL AND OTHER REQUIREMENTS................................86 5.4.1. Environmental Requirements.....................................................................................86 5.4.2. Mechanical Requirements..........................................................................................88 5.4.3. Current Rating Requirement......................................................................................89 5.4.4. Additional Considerations..........................................................................................89 6. ADD-IN CARD FORM FACTORS AND IMPLEMENTATION....................................91 6.1. ADD-IN CARD FORM FACTORS...........................................................................................91 6.2. CONNECTOR AND ADD-IN CARD LOCATIONS.............................................................104 6.3. CARD INTEROPERABILITY................................................................................................110 A. INSERTION LOSS VALUES (VOLTAGE TRANSFER FUNCTION) (INFORMATIONAL ONLY).............................................................................................113 ACKNOWLEDGEMENTS......................................................................................................117 4 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.12.0 Figures FIGURE 1-1: VERTICAL EDGE-CARD CONNECTOR.................................................................13 FIGURE 1-2: EXAMPLE SERVER I/O BOARD WITH PCI EXPRESS SLOTS ON A RISER.....13 FIGURE 2-1: DIFFERENTIAL REFCLK WAVEFORM.................................................................16 FIGURE 2-2: EXAMPLE CURRENT MODE REFERENCE CLOCK SOURCE TERMINATION17 FIGURE 2-3: SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING.............................................................................................................................19 FIGURE 2-4: SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT..........20 FIGURE 2-5: SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING...............................................................................................................................20 FIGURE 2-6: DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD20 FIGURE 2-7: DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME..........20 FIGURE 2-8: DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK.............................21 FIGURE 2-9: REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING.......21 FIGURE 2-10: POWER UP................................................................................................................24 FIGURE 2-11: POWER MANAGEMENT STATES.........................................................................26 FIGURE 2-12: OUT-OF-TOLERANCE THRESHOLD WINDOWS...............................................27 FIGURE 2-13: POWER DOWN.........................................................................................................28 FIGURE 2-14: WAKE# RISE AND FALL TIME MEASUREMENT POINTS...............................36 FIGURE 3-1: PRESENCE DETECT IN A HOT-PLUG ENVIRONMENT......................................38 FIGURE 4-1: PCI EXPRESS ON THE SYSTEM BOARD...............................................................43 FIGURE 4-2: PCI EXPRESS CONNECTOR ON SYSTEM BOARD WITH AN ADD-IN CARD.43 FIGURE 4-3: PCI EXPRESS CONNECTOR ON A RISER CARD WITH AN ADD-IN CARD....44 FIGURE 4-4: LINK DEFINITION FOR TWO COMPONENTS......................................................45 FIGURE 4-5: JITTER BUDGET........................................................................................................48 FIGURE 4-6: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE DIAGRAM............54 FIGURE 4-7: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE DIAGRAM............57 FIGURE 4-8: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR ADD-IN CARD RECEIVER PATH COMPLIANCE..........................................................................................58 FIGURE 4-9: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR ADD-IN CARD RECEIVER PATH COMPLIANCE..........................................................................................60 FIGURE 4-10: SYSTEM BOARD TRANSMITTER PATH COMPOSITE COMPLIANCE EYE DIAGRAM.................................................................................................................................61 FIGURE 4-11.......................................................................................................................................62 : TWO PORT MEASUREMENT FUNCTIONAL BLOCK DIAGRAM..........................................63 FIGURE 4-12: SYSTEM BOARD TRANSMITTER PATH COMPOSITE COMPLIANCE EYE DIAGRAM.................................................................................................................................65 FIGURE 4-13: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR SYSTEM BOARD RECEIVER PATH COMPLIANCE..........................................................................................67 FIGURE 5-1: CONNECTOR FORM FACTOR.................................................................................75 FIGURE 5-2: RECOMMENDED FOOTPRINT................................................................................77 FIGURE 5-3: ADD-IN CARD EDGE-FINGER DIMENSIONS.......................................................79 FIGURE 5-4: ILLUSTRATION OF ADJACENT PAIRS.................................................................84 FIGURE 5-5: CONTACT RESISTANCE MEASUREMENT POINTS............................................87 FIGURE 6-1: STANDARD HEIGHT PCI EXPRESS ADD-IN CARD WITHOUT THE I/O BRACKET.................................................................................................................................92 FIGURE 6-2: STANDARD HEIGHT PCI EXPRESS ADD-IN CARD WITH THE I/O BRACKET AND CARD RETAINER...........................................................................................................93 FIGURE 6-3: ADDITIONAL FEATURE AND KEEPOUTS ON THE X16 GRAPHICS CARD...94 5 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.12.0 FIGURE 6-4: STANDARD ADD-IN CARD I/O BRACKET...........................................................95 FIGURE 6-5: BRACKET DESIGN WITH THE MOUNTING TABS MOUNTED ON THE PRIMARY SIDE OF THE ADD-IN CARD..............................................................................96 FIGURE 6-6: ADD-IN CARD RETAINER.......................................................................................97 FIGURE 6-7: LOW PROFILE PCI EXPRESS ADD-IN CARD WITHOUT THE I/O BRACKET100 FIGURE 6-8: LOW PROFILE PCI EXPRESS ADD-IN CARD WITH THE I/O BRACKET.......101 FIGURE 6-9: LOW PROFILE I/O BRACKET................................................................................102 FIGURE 6-10: FULL HEIGHT I/O BRACKET FOR LOW PROFILE CARDS............................103 FIGURE 6-11: EXAMPLE OF A PC SYSTEM IN MICROATX FORM FACTOR......................104 FIGURE 6-12: INTRODUCTION OF A PCI EXPRESS CONNECTOR IN A MICROATX SYSTEM..................................................................................................................................105 FIGURE 6-13: MORE PCI EXPRESS CONNECTORS ARE INTRODUCED ON A MICROATX SYSTEM BOARD...................................................................................................................106 FIGURE 6-.........................................................................................................................................107 14: PCI EXPRESS CONNECTOR LOCATION IN A MICROATX SYSTEM WITH ONE PCI EXPRESS CONNECTOR................................................................................................108 FIGURE 6-15: PCI EXPRESS CONNECTOR LOCATION IN A MICROATX SYSTEM WITH TWO PCI EXPRESS CONNECTORS....................................................................................109 FIGURE 6-16: CARD ASSEMBLED IN CONNECTOR................................................................110 FIGURE A-1: EXAMPLE INTERCONNECT TERMINATED AT THE CONNECTOR INTERFACE............................................................................................................................113 FIGURE A-2: INSERTION LOSS BUDGETS................................................................................114 6 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.12.0 Tables TABLE 2-1: REFCLK DC SPECIFICATIONS AND AC TIMING REQUIREMENTS..................18 TABLE 2-2: MAXIMUM ALLOWED PHASE JITTER WHEN APPLIED TO FIXED FILTER CHARACTERISTIC..................................................................................................................22 TABLE 2-3: AUXILIARY SIGNAL DC SPECIFICATIONS - PERST#, WAKE#, AND SMBUS 35 TABLE 2-4: POWER SEQUENCING AND RESET SIGNAL TIMINGS.......................................36 TABLE 4-1: POWER SUPPLY RAIL REQUIREMENTS................................................................39 TABLE 4-2: ADD-IN CARD POWER DISSIPATION.....................................................................40 TABLE 4-3: TOTAL SYSTEM JITTER BUDGET FOR 2.5 GT/S SIGNALING............................49 TABLE 4-4: ALLOCATION OF INTERCONNECT JITTER BUDGET FOR 2.5 GT/S SIGNALING..............................................................................................................................49 TABLE 4-5: TOTAL SYSTEM JITTER BUDGET FOR 5 GT/S SIGNALING...............................50 TABLE 4-6: ALLOWABLE INTERCONNECT LANE-TO-LANE SKEW.....................................51 TABLE 4-7: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE REQUIREMENTS AT 2.5 GT/S.....................................................................................................................................53 TABLE 4-8: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE REQUIREMENTS AT 5 GT/S AND 3.5 DB DE-EMPHASIS.......................................................................................54 TABLE 4-9: ADD-IN CARD JITTER REQUIREMENTS FOR 5 GT/S SIGNALING AT 3.5 DB DE-EMPHASIS..........................................................................................................................55 TABLE 4-10: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE REQUIREMENTS AT 5 GT/S AT 6.0 DB DE-EMPHASIS....................................................................................55 TABLE 4-11: ADD-IN CARD JITTER REQUIREMENTS FOR 5 GT/S SIGNALING AT 6.0 DB DE-EMPHASIS..........................................................................................................................57 TABLE 4-12: ADD-IN CARD MINIMUM RECEIVER PATH SENSITIVITY REQUIREMENTS AT 2.5 GT/S...............................................................................................................................57 TABLE 4-13: ADD-IN CARD MINIMUM RECEIVER PATH SENSITIVITY REQUIREMENTS AT 5 GT/S..................................................................................................................................59 TABLE 4-14: SYSTEM BOARD TRANSMITTER PATH COMPLIANCE EYE REQUIREMENTS AT 2.5 GT/S...............................................................................................................................60 TABLE 4-15: SYSTEM BOARD TRANSMITTER PATH COMPLIANCE EYE REQUIREMENTS AT 5 GT/S..................................................................................................................................64 TABLE 4-16: SYSTEM BOARD JITTER REQUIREMENTS FOR 5 GT/S SIGNALING.............65 TABLE 4-17: SYSTEM BOARD MINIMUM RECEIVER PATH SENSITIVITY REQUIREMENTS AT 2.5 GT/S...............................................................................................65 TABLE 4-18: SYSTEM BOARD MINIMUM RECEIVER PATH SENSITIVITY REQUIREMENTS AT 5 GT/S FOR A LINK THAT OPERATES WITH 3.5 DB DE- EMPHASIS................................................................................................................................66 TABLE 4-19: SYSTEM BOARD MINIMUM RECEIVER PATH SENSITIVITY REQUIREMENTS AT 5 GT/S FOR A LINK THAT OPERATES WITH 6.0 DB DE- EMPHASIS................................................................................................................................67 TABLE 5-1: PCI EXPRESS CONNECTORS PINOUT....................................................................69 TABLE 5-2: SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES FOR 2.5 GT/S SUPPORT..................................................................................................................................82 TABLE 5-3: SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES FOR 5 GT/S SUPPORT..................................................................................................................................85 TABLE 5-4: TEST DURATIONS......................................................................................................87 TABLE 5-5: MECHANICAL TEST PROCEDURES AND REQUIREMENTS..............................88 TABLE 5-6: END OF LIFE CURRENT RATING TEST SEQUENCE............................................89 7 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.12.0 TABLE 5-7: ADDITIONAL REQUIREMENTS...............................................................................89 TABLE 6-1: ADD-IN CARD SIZES..................................................................................................91 TABLE 6-2: CARD INTEROPERABILITY....................................................................................110 TABLE A-1: ALLOCATION OF INTERCONNECT PATH INSERTION LOSS BUDGET FOR 2.5 GT/S SIGNALING...................................................................................................................114 8 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.12.0 1 1. Introduction This specification is a companion for the PCI Express Base Specification, Revision 1.12.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form 5 factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications. 1.1. Terms and Definitions Addadd-in card A card that is plugged into a connector and mounted in a chassis slot. ATX A system board form factor. Refer to the ATX Specification, 10 Revision. 2.2. ATX-based form factor Refers to the form factor that does not exactly conform to the ATX specification, but uses the key features of the ATX, such as the slot spacing, I/O panel definition, etc. Auxiliary signals Signals not required by the PCI Express architecture but necessary 15 for certain desired functions or system implementation, for example, the SMBus signals. Basic bandwidth Contains one PCI Express Lane x1, x2, x4, x8, x12, x16 x1 refers to one PCI Express Lane of basic bandwidth; x4 refers to a collection of four PCI Express Lanes; etc. 20 Card Interoperability Ability to plug a PCI Express card into different Link connectors and the system works, for example, plugging a PCI Express x1 I/O card into a x16 graphics slot. Down-plugging Plugging a larger Link card into a smaller Link connector; for example, plugging a x4 card into a x1 connector 25 Down-shifting Plugging a PCI Express card into a connector that is not fully routed for all of the PCI Express Lanes; for example, plugging a x4 card into a x8 capable connector with only four Lanes being routed Evolutionary strategy A strategy to develop the PCI Express connector and card form 30 factors within today’s chassis and system board form factor infrastructure constraints. High bandwidth Supports larger number of PCI Express Lanes, such as a x16 card or connector. 9 PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.12.0 Hot-Plug Insertion and/or removal of a card into an active backplane or system board as defined in PCI Standard Hot-Plug Controller and Subsystem Specification, Revision. 1.0. No special card support is required. Hot swap Insertion and/or removal of a card into a passive backplane. The 5 card must satisfy specific requirements to support Hot swap. Interoperability Ability to plug a PCI Express card into different Link connectors and the system works, for example, plugging a x1 PCI Express I/O card into a x16 graphics slot. Link A collection of one or more PCI Express Lanes 10 Low profile card An add-in card whose height is no more than 68.90 mm (2.731 inches) microATX An ATX-based system board form factor. Refer to the microATX Motherboard Interface Specification, Revision 1.2. PCI Express Mini Card PCI Express for mobile form factor, similar to Mini PCI 15 PCI Express Lane One PCI Express Lane contains two differential lines for Transmitter and two differential lines for Receiver. A by-N Link is composed of N Lanes. Receiver path The path from the connector to the receiver for a differential data pair (system) or the edge finger to the receiver (add-in card). 20 sideband signaling A method for signaling events and conditions using physical signals separate from signals forming the Link between two components. Standard height card An add-in card whose height is no more than 111.15 mm (4.376 inches) 25 Transmitter path The path from the transmitter to the connector for a differential data pair (system) or the transmitter to the edge finger (add-in card). Up-plugging PlugPlugging a smaller Link card into a larger Link connector; for example, plugging a x1 card into a x4 connector wakeup A mechanism used by a component to request the reapplication of 30 main power when in the L2 Link state. Two such mechanisms are defined in the PCI Express Base Specification, Revision 1.1: 2.0: Beacon and WAKE#. This specification requires the use of WAKE# on any add- in 35 card or system board that supports wakeup functionality. 1.2. Reference Documents This specification references the following documents: (cid:137) PCI Express Base Specification, Revision 1.12.0 (cid:137) PCI Local Bus Specification, Revision 3.0 (cid:137) PCI Express Jitter Modeling 40 (cid:137) PCI Express Jitter and BER 10