Parallel JPEG Processing with a Hardware Accelerated DSP Processor Examensarbete utfo¨rt i Datorteknik vid Tekniska Ho¨gskolani Link¨oping av Mikael Andersson, Per Karlstro¨m Reg nr: LiTH-ISY-EX-3548-2004 Linko¨ping 2004 Parallel JPEG Processing with a Hardware Accelerated DSP Processor Examensarbete utfo¨rt i Datorteknik vid Tekniska Ho¨gskolani Link¨oping av Mikael Andersson, Per Karlstro¨m Reg nr: LiTH-ISY-EX-3548-2004 Supervisor: Dake Liu Examiner: Dake Liu Linko¨ping 19th October 2004. Avdelning, Institution Datum Division, Department Date 2004−05−03 Institutionen för systemteknik 581 83 LINKÖPING Språk Rapporttyp ISBN Language Report category Svenska/Swedish Licentiatavhandling ISRN LITH−ISY−EX−3548−2004 X Engelska/English X Examensarbete C−uppsats Serietitel och serienummer ISSN D−uppsats Title of series, numbering Övrig rapport ____ URL för elektronisk version http://www.ep.liu.se/exjobb/isy/2004/3548/ Titel Parallell JPEG behandling med en hårdvaruaccelerarad DSP−processor Title Parallel JPEG Processing with a Hardware Accelerated DSP Processor Författare Mikael Andersson, Per Karlström Author Sammanfattning Abstract This thesis describes the design of fast JPEG processing accelerators for a DSP processor. Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co−processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed. First a decoder and an encoder were implemented in DSP assembler. The cycle consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioral models of the accelerators were then written in C++ and the assembly code was modified to work with the new hardware. Finally, the accelerators were implemented using Verilog. Extension of the accelerator instructions was given following a custom design flow. Nyckelord Keyword JPEG, JFIF, 2−D DCT, Huffman, Accelerator, HW/SW partitioning Abstract This thesis describes the design of fast JPEG processing accelerators for a DSP processor. Certain computation tasks are moved from the DSP processor to hardware ac- celerators. The accelerators are slave co-processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clockcyclesandseveraltaskscanruninparallel. Thiswillreducethetotalnumber of clock cycles needed. First a decoder and an encoder were implemented in DSP assembler. The cyc- le consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioralmodels of the accelerators were then written in C++andtheassemblycodewasmodi(cid:12)edtoworkwiththenewhardware. Finally, the accelerators were implemented using Verilog. Extension of the accelerator instructions was given following a custom design flow. Keywords: JPEG,JFIF,2-DDCT,Hu(cid:11)man,Accelerator,HW/SWpartitioning. i ii Acknowledgment We would like to thank our supervisor and examiner Professor Dake Liu for guid- ance and support during the project. We would also like to thank opponents, Claes Hedlund and Mats Karlsson for many useful comments on our thesis. iii iv