Optimize Your SAR ADC Design Bonnie Baker Senior Applications Engineer [email protected] Special Thanks for Inputs from Tim Green Rick Downs Miro Oljaca The most popular and versatile Analog-to-Digital Converter (ADC) has a Successive Approximation Register (SAR) topology. These converters work by comparing an analog voltage signal to known fractions of the full-scale input voltage and then setting or clearing bits in the ADC’s data register. Modern SAR converters use a Capacitive Data Acquisition Converter (C-DAC) to successively compare bit combinations. Usually these devices have an integrated sample/hold input function. It is common to use an operational amplifier (Op Amp) to directly drive the input of a SAR Analog-to-digital converter (SAR-ADC). Although this configuration is an acceptable practice in manufacturer’s data sheets, it has the potential to create circuit performance limitations. For optimum performance, C-DAC SAR-ADCs require the correct front-end buffer and filter. The additional input filter or RC- network will relax the driving Op Amp requirements. This presentation details the reasons for an input filter and buffer amplifier to the C-DAC SAR-ADC along with an analytical approach to selecting the filter components and op amp characteristics. 1 SAR ADC System Design Op Amp A/D - Filter SAR D OUT + V S OpAmp Filter ADC Signal Bandwidth Charge Reservoir Acquisition Time Slew Rate Capacitor Load Data Rate Isolation Output Impedance Resolution Noise Filtering ADC Input Topology ADC Ref In A typical input stage for a SAR ADC system is shown above. A buffer amplifier is used, driving a small RC-filter prior to the input to the ADC. We’ll examine just what these elements do for us in this seminar. Each of these elements have a relationship to the preceding or the following element which will make the combination more powerful than the individuals. As we can see, for each part of this circuit, there are many considerations, all of which potentially affect the accuracy and resolution of the system. When choosing components for this system, we must be mindful of all of these considerations. 2 The Design Tools We Will Use • Data Sheet Parameters . • Rules of Thumb . • Tricks and Tips . • Testing . Many articles have been written about choosing op amps for use in driving ADCs (see last page of this presentation). All of the articles point out things that we should watch out for. From these articles and this seminar, we will observe some guidelines and make it easier and faster to get to a good design. The design procedure we will present contains some rigorous analysis, but also observes rules of thumb, some “tricks”, and of course refers to the datasheets of the products in our circuit. As always with analog circuitry and proof of function will be required with some testing and prototyping. 3 Design Procedure +V +V CC REF Op Amp A/D - Filter D + R CFLT 0 V OUT FLT ? ? ? ? V S A E D C B Signal (1) Op amp (5) RC pair (3,4) ADC (2) Bandwidth Input Stage ADC vs cap Full-scale input range Full-scale Bandwidth Cap quality Acquisition time Range Output R Opa vs Resistor Kick Back Voltage & O Settling Time Charge So this is how we design our SAR-ADC circuit from beginning to end. We will first determine what our input signal looks like in terms of the bandwidth and a full-scale range. Once we understand the characteristics of our input signal, we will take a look at the ADC. The ADC that we select should match the bandwidth of our input signal per nyquist. This device should also have an appropriate resolution for our signal. With the ADC selected, we will determine the acquisition time and the ADC sampling capacitance. Once we’ve selected our ADC, we determine the values of the external input capacitance (C ) and input resistance (R ). We will find that the quality of our FLT FLT capacitor is critical if we are concerned about the distortion that will be generated by our circuit. The value of our capacitor insurers that our ADC will have ample charge for each conversion. The value of the resistor insurers that our operational amplifier will be stable. We will finally select our operational amplifier. At this point, we will determine what style of the input stage we need. we will also select an amplifier that has ample bandwidth for the input signal. 4 1. Define Input Signal +V +V CC REF Op Amp A/D - Filter D + R CFLT 0 V OUT FLT V S A E D C B • Highest Frequency – 1 kHz (single channel) • Largest Voltage Swing – 0 to 4.096 V • High Accuracy – 62.5 μV LSB size or 16-bit with range of 4.096 These are characteristics of the input signal that we will use in our discussion of our circuit. The highest input frequency in our SAR-ADC system is 1 kHz. The largest voltage swing of our ADC should be able to handle on its input from 0 to 4.096V. We want to have 16-bit resolution or a 62.5 μV LSB size to our analog signal. We will design the entire system around these specifications. 5 2. Selecting the ADC +V +V CC REF Op Amp A/D - Filter + R CFLT 0 V DOUT FLT V S A E D C B • Things we need to know – Sampling frequency > 50 ksps – Full-scale input range (FSR) = 4.096V – Highest Resolution : 16-bit – SAR Architecture : no latency Once we know the pertinent characteristics of the input signal we can select the ADC for this circuit. In particular, we want an ADC that has a minimum sampling frequency that is two times higher than the maximum signal frequency plus an additional 10 to 20 x multiplier so that we capture a better picture of the input signal. With this logic we will need an ADC that has a maximum sampling frequency of at least 20 ksps. Given the sampling rate of > 20 ksps, the appropriate architecture for this application circuit is a SAR converter. We will use a SAR architecture for its low latency, and chose this particular converter architecture because it offers the highest speed and resolution combination of converters that operate at this sampling speed. 6 ADS8320 Application Specs • 16-bit, 100 kHz Micropower, Sampling Analog- To-Digital Converter – Throughput Rate (Sampling Rate) = 100 ksps • t = 1.88 μs ACQ (min) – Input V = V = +4.096 V FSR REF – C (input sample hold capacitance) = 45 pF SH • Secondary specifications – SNR = 88 dB @ 1 kHz – THD = -86 dB @ 1 kHz – SINAD = 84 dB @1 kHz – SFDR = 86 dB @1 kHz For the TI product line, the ADS8320 best matches our input requirements. This slide shows some of the important ADS8320 specifications we’ll need to know. Fortunately, all of these parameters are specified in the datasheet. The maximum throughput rate of the ADS8320 at 100 ksps exceeds the >20 ksps requirement. The input range of the ADS8320 is equal to the reference voltage supplied to the converter. A 4.096 reference voltage is recommended. Specifications that we are going to need through out the remainder of this discussion is the signal acquisition time (t = 1.88 μs) ACQ and the value of the input capacitance of the SAR converter. In the case of the ADS8320, the input capacitance (C ) is equal to 45 pF. SH Secondary specifications, such as Signal-to-Noise Ratio (SNR), Total harmonic Distortion (THD), Signal-to-Noise Ratio plus Noise (SINAD), and Spurious Free Dynamic Range are specifications that we will keep our eye on as we proceed through the design. 7 A/D Converter Terms • Acquisition Time (t ): ACQ – The time the internal A/D sample capacitor is connected to the A/D input analog signal • Conversion Time (t ) CONV – The time the A/D requires to convert the sampled analog input to a digital output after the acquisition time (t ) is complete ACQ • Throughput Rate [Sampling Rate] – Maximum frequency at which A/D conversions can be repeated – Is equal to the Acquisition time plus the Conversion time (t ACQ + t ) CONV • i.e. 100 ksps Throughput Rate [Sampling Rate] implies that an input analog signal may be converted every 10μs Before going further, it’s important to understand some of the timing characteristics of the ADC that we’ll be using. A SAR ADC takes a sample of a signal at a moment in time, and converts that one sample to a digital value. It takes a certain amount of time for the input signal to be connected to the internal capacitor of the ADC and store its voltage on the internal sampling capacitor. The amount of time allowed to get the input voltage stored on the ADC input capacitor to the accuracy required by the ADC is the acquisition time of the converter. Once the sample voltage is stored on the sampling capacitor, the actual conversion process takes place, where the sample is successively compared to known fractions of charge. The time it takes to make all of the comparisons and generate the digital value is the conversion time. To accomplish a complete conversion, both the acquisition and conversion times must pass. The fastest a system can sample and convert a signal would be the rate at which it can successively sample. The throughput rate of a converter describes the fastest speed that the ADC can successively sample. This rate must also include the settling time of the converter’s input stage, as well as settling times for the other amplifiers and elements in the signal chain. 8 SAR Acquisition and Conversion Time VS Data Output Register ½LSB V (t) CSH t ACQ V SH0 t0 tACQ R = 0Ω RSW Time S - SAR V S1 S + C SH N-bit search DAC A typical SAR conversion cycle has two phases; a sampling phase and a conversion phase. During the sampling phase, the analog input signal charges the ADC’s Sample-and-Hold (S/H) capacitor (C ) through the switch resistance (R ) to a level proportional to the SH SW analog input. The combination of the switch resistance (R ), the source resistance (R ), SW S and the sampling capacitor (C ) determine the rate of change of the charge on the sampling SH capacitor (C ). SH The diagram in the upper left portion of this slides illustratesthe rise time characteristics of the voltage on C during the acquisition phase. As expected, this rise time has asingle pole SH response. Conversion begins immediately following the sampling phase with the opening of the input switch (S1). Conversion successively compares the unknown value of the charge stored on the S/H capacitor to known fractions of charge. After each comparison, logic on the ADC determines if the unknown charge is greater or smaller than the known fractional charge. At the end of the process the data register will contain a binary value proportional to the value initially placed on the S/H capacitor. The user reads thisvalue out as converted data. As shown in the diagram above, the converter we are evaluating does not have an internal input buffer amplifier. This may not be the case with the particular SAR converter you may use. The product data sheet provides details on the input structure for a particular product. 9 Single-pole, Time Constant Multiplier Time Constant Number of bits 0.5LSB (k) Multiplier 10 0.0488281% 8 12 0.0122070% 9 14 0.0030518% 11 16 0.0007629% 12 18 0.0001907% 13 20 0.0000477% 15 22 0.0000119% 17 24 0.0000030% 18 The amount of time needed to settle the input structure of the SAR-ADC depends on the number of bits of the converter. This table lists the number (k) of time constants (τ) required to settle to within a half LSB to a given number of bits. For our 16-bit example, we will allow the twelve time constants for the ADC input stage to settle or k =12. The time constant of the ADS8320 alone is equal to R (~100 Ω) SW times C (= 45 pF, typ) or τ = C x R = 4.5 ns. The input structure of the SH ADC SH SW ADC requires a total of k x τ time or 540 ps to charge. When we add the external ADC RC network before the ADC, the time constant of the system will change to become τ which equals C times R . FLT FLT FLT 10