-C? -C/3 NASA Technical Memorandum 106424 AIAA-94-1160 QPPM Receiver for Free-Space Laser Communications J.M. Budinger, J.H. Mohamed, and L.A. Nagy National Aeronautics and Space Administration Lewis Research Center Cleveland, Ohio P.J. Lizanich Analex Corporation Brook Park, Ohio and D.J. Mortensen Sverdrup Technology, Inc. Lewis Research Center Group Brook Park, Ohio Prepared for the 15th International Communications Satellite Systems Conference sponsored by the American Institute of Aeronautics and Astronautics San Diego, California, February 28-March 3, 1994 NASA QPPM RECEIVER FOR FREE-SPACE LASER COMMUNICATIONS J. M. Budinger, J. H. Mohamed, L. A. Nagy National Aeronautics and Space Administration Lewis Research Center Cleveland, Ohio 44135 P. J. Lizanich D. J. Mortensen Analex Corporation Sverdrup Technology, Inc. Brook Park, Ohio 44142 Brook Park, Ohio 44142 Abstract also developed the electronics for high data rate applications of free-space communications using optical carriers. Laser communications offers the potential of A prototype receiver developed at NASA Lewis Research significantly higher destination power flux density than rf center for direct detection and demodulation of quaternary communications in point-to-point free-space applications pulse position modulated (QPPM) optical carriers is due to more precisely focused beams. If the system cost described. The receiver enables dual-channel is competitive with rf solutions, direct detection of pulse communications at 325-Megabits per second (Mbps) per modulated laser light may be used to link future channel. The optical components of the prototype receiver constellations of tens or hundreds of commercial satellites are briefly described. The electronic components, in low Earth orbits. NASA relay satellites in geostationary comprising the analog signal conditioning, slot clock orbits and deep-space planetary probes may also require recovery, matched filter and maximum likelihood data the high capacity (over 1-Gbps) links that laser recovery circuits are described in more detail. A novel communications afford. digital symbol clock recovery technique is presented as an alternative to conventional analog methods. Simulated link This paper describes the prototype receiver developed at degradations including noise and pointing-error induced Lewis for detection and demodulation of quaternary pulse amplitude variations are applied. The bit-error-rate position modulated (QPPM) signals. Under the high- performance of the electronic portion of the prototype speed laser integrated terminal electronics (Hi-LITE) receiver under varying optical signal-to-noise power ratios project, Lewis has constructed a dual-channel QPPM is found to be within 1.5-dB of theory. Implementation of transmitter and receiver operating at 325 Megabits per the receiver as a hybrid of analog and digital application second (Mbps) per channel. Figure 1 shows a photograph specific integrated circuits is planned. of the Hi-LITE racks plus special test equipment. The initial concept for the project including a description Introduction of the communications electronics and computer controlled special test and demonstration equipment was reported in Beginning in the early 1980's, NASA's Lewis Research an earlier paper'. Since that time, several changes have Center (Lewis) has conducted a space communications been made to the functional designs and implementation technology development program for commercial approaches. This paper reviews the final optical, analog, applications of higher radio frequency (ro bands such as and digital hardware implementation of the prototype Ka (20- to 30-GHz). Over the past three years, Lewis has receiver and summarizes its performance. A companion paper'- reviews the prototype transmitter, and discusses the implementation and testing issues encountered during its Copyright m 1993 by the American Institute of Aeronautics and development. A future paper will describe the capabilities Astronautics, Inc. No copyright is asserted in the United States under of the automated special test equipment and present final Title 17, U.S. Code. The U.S. Government has a royalty-free license to exercise all rights under the copyright claimed herein for Government test results for a wide range of simulated operating purposes. All other rights are reserved by the copyright owner. conditions. n In the following sections of this paper, individual subsystems of the prototype receiver are discussed. Figure 2 shows a functional block diagram of the entire receiver. The optical receiver, including the avalanche photodiode (APD) and preamplifier, is presented first. Next, the receiver's front-end analog electronics, including signal conditioning, slot clock recovery, matched filter data recovery, and maximum likelihood detection are discussed. Then, the digital electronics for symbol clock recovery and data decoding and demultiplexing are described. Some test results are presented for the prototype receiver operating under both an rf and optical simulation of actual intersatellite links. The paper concludes with a statement of future plans for the project. Quaternary Pulse Position Modulation Recall that QPPM is one of a family of M-ary pulse position modulation formats, where k=log,M bits of information are conveyed in each symbol. In QPPM, M=4, and therefore k=2 bits per symbol. Figure 1.-- HAITE system. (left to right: video rack, special test equipment, electronics, and computer). CLOCK RECOVERY .oyery 1 I^recovery ;A AvoaWlordti<ohdee Pre "P "P^ rWe alenr . HWulan"lgyadi n• PoM amp •dPNtvdeire,' rA/gFid ' +irteeJd' . "^^ dOecPoPdMe r DAata Darn sA B Avatgord>cghdee I P,e amp •PrimeaAaercrD. • ^tpnt9rda.n Fbstamp. Wte .Idke-e te^ic wloor decoder pate ®B OPTKS OPTICAL RECENER ANALOG SIGNAL COND(TCNER DATA RECOVERY dock Data 2 Bit de- 2 Chanrbl ply gER test A vrlwleaver data rnu re5d.er iecener S nk to Dagta 2 inBteirl ldeaev-e r 2 dCahtaa rmnaerlt Arensb &elry nYod efoor Marked bares ndicate arubq cacwhy Clock DIGRAL DATA ROUTER DATA SWKS Figure 2.--Block diagram of Hi-LITE dual-channel QPPM receiver. 2 Figure 3 shows the mapping of each group of two photograph of the optical STE rack, designed and information bits into one of the four possible QPPM fabricated by NASA Goddard Space Flight Center. The symbols used in Hi-LITE. optics, including the laser, filter, and APD are located in the top portion of the rack. The primary function of the optical receiver is to convert the detected modulated laser beam to an electrical waveform using the APD. The beams, each in the 810-830 nm wavelength range, are Binary data bits QPPM symbols separated by at least 10 nm. The APD is sensitive to a relatively large range of wavelengths, so an interference b, - - t filter with a passband centered at the laser frequency is inserted to prevent optical channel crosstalk. The filter 0 0 also blocks laser noise emission and broadband 0 1 background solar and stellar radiation in an operational 1 0 —^ system. Following the filter is a focusing lens, used to concentrate the incident laser beam upon a detector area 1 1 / of about 3 x 10-` cm'-. The development of high speed, high sensitivity APD's is Figure 3.—Encoding binary data into QPPM symbols critical for free-space laser links. For optimum performance, a state-of-the-art hybrid package, combining a high-sensitivity APD and a preamplifier is required. One A maximum of 650-Mbps of source data are demultiplexed such package is a 900-MHz, 128 amp/watt optical receiver onto two channels at 325-Mbps each. The timing for made by EG&G for NASA Goddard Space Flight Center. binary information bits and QPPM symbols along with their synchronized clocks is shown in figure 4. 3.08 ns Si;­ yy W.: 1325-Mbosl. 3.08 ns &nary clock 1325-MHt. 6.15 u OPPM symbols (162.5-MsOs). F--y $bi UOCk (650-MHy. Figure 4.—Timing relationship of binary source data, QPPM, and clocks. Optical Receiver In an actual intersatellite link, two 325-Mbps QPPM encoded laser beams (A and B) would impinge on a telescope and then be directed to the optical receiver. In the laboratory configuration at Lewis, the space link, the telescope, and associated optics are replaced by optical special test equipment (STE) whose main component is a variable density optical filter. Only one channel (one laser beam) is simulated with this STE. Figure 5 shows a Figure 5.--Optical special test equipment rack. A Newport model 877 APD having a greater bandwidth The AGC circuit consists of a variable gain control (VGC) (1.7-GHz) but less sensitivity (02 amp/watt) than the amplifier having a dynamic range of 35-dB and a 3-dB EG&G unit was available for use in the Hi-LITE project. bandwidth from 100-KHz to 2.5-GHz. A low-pass filter This APD was coupled to a 2.0-dB noise figure attenuating unwanted high frequency noise feeds a power preamplifier to increase the signal amplitude. divider. One output of the divider goes to a detector producing a feedback signal to be amplified and filtered by two operational amplifier circuits, resulting in a 0- to -5- Analog Circuits volt control input to the VGC amplifier. The other output of the power divider is routed through In a satellite link, the low level signals out of the optical two linear amplifiers to compensate for signal splitting receiver exhibit link degradations including pointing-error losses, then further divided (three ways) to provide signals induced amplitude variations (with an expected dynamic for slot clock and data recovery and a test output. At this range of 35-dB at up to 1-KHz), noise, and timing jitter. point in the circuit the binary waveform amplitude is fairly These signals are not suitable for digital processing at constant at a nominal level of 0.5-volts peak-to-peak. standard logic levels, and must therefore be conditioned by analog circuitry, indicated by the marked boxes in figure 2, Slot clock recovery is obtained with a Broadcast and shown in greater detail in figure 6. The analog signal Communications Products (BCP) model 50-b bit- conditioning circuitry compensates for degradations and synchronizer module. It generates a slot clock (650-MHz) rapid power fluctuations in the received signal using and a synchronized digital logic level representation of the amplifiers, automatic gain control (AGC), and filters to QPPM waveform obtained by straightforward threshold provide uniform level outputs to be used by the clock and comparison. This first-order approximation of the data recovery circuits that follow. transmitted waveform is used by subsequent circuitry to recover symbol clock timing (discussed in the digital The first element of the analog signal conditioner is a circuits section), but not for final data recovery. limiting amplifier to protect vulnerable components from damage due to excessive voltage (up to 4-volts). The Only one bit synchronizer module (on channel A) is normal operating input signal range is from 1 to 100-mv. required as long as the timing skew between channels A In addition, the limiting amplifier has a low noise figure and B can be maintained within one-half of one slot period (2.8-dB), which greatly influences the 4.5-dB noise figure (+/-769-ps). The clock is then buffered and distributed to of the entrie signal conditioner subsystem. The attenuator be used by both channels throughout the receiver. ensures that the signal feeding the AGC circuit stays within prescribed limits. U"lo q 6 dB 1—tA. Gs. lo.' Asa Pb FYI^r 0.— FRE^MPU Gi nPV AND UM/nNO ......................... ° AUMAM nC CAW CYWrROL ............................................................. POSr A WPL4QER5 AND CLOC X< 1 D4 rA RECOVERY .... ...................................................................................... . Figure 6.--Analog electronics subsystem. 4 Altemate methods of data recovery were investigated and its maximum. However, only one out of every four sets of implemented to enhance the performance of those comparisons represents a valid 4-slot QPPM symbol. The reported in an earlier paper'. As shown in figure 6, an task of determining the correct phase to establish the output of the 3-way power divider is used to feed a proper symbol boundaries is performed by the symbol matched filter and other components of the data recovery clock recovery circuit, described in the following section. circuit. For the matched filter, three versions of 4-tap delay line integrators and low pass filters were implemented, using analog delay lines, coaxial delay modules, and microstrip circuits. Each was physically large and worked better with ideal rectangular pulses than the more trapezoidal pulses obtained in the actual system. An alternative matched filter consists of a 7th order Bessel low-pass filter that approximates a raised cosine response rather than a triangular output waveform that would be produced by an ideal matched filter with rectangular input pulses. This approximation has been shown by Sun` to be a practical alternative to an ideal matched filter when using components with limited electrical bandwidth. In theory, the ideal matched filter gives optimal BER performance since it gives maximum signal-to-noise ratio (SNR) at its output when the input PPM pulse shape is rectangular. However, the matched filter is not the optimal filter for non-rectangular PPM pulse shapes created by lasers and electronics with less than infinite bandwidth and degraded by non-additive white Gaussian noise (AWGN). The bandwidth of the laser, APD, preamplifier, and all electronics prior to the matched filter must be greater than 2/r, (where r, is one PPM slot) to obtain an ideal triangular matched filter response. By using a raised cosine filter, the bandwidth requirements of the laser APD preamplifier and electronics can be reduced by nearly half (about 1/r,) while the BER is still very nearly the same as that using a matched filter. A low-pass Bessel filter of seventh-order, with a 3-dB cutoff frequency of 845-MHz, approximates the desired equalizer output. Figure 7 shows the effect of the analog signal conditioning Figure 7.--Analog signal conditioning waveforms: (top) input circuits, including the matched filter, on an input signal of signal, (bottom) amplified matched filter output. 8-dB E,/N. with 12-dB 1000-Hz amplitude variation. The significantly improved signal is suitable for input to the digital receiver circuits. However, the contribution of the Digital circuits matched filter alone was found to be negligible mainly due to bandwidth limitations of upstream components. The digital circuitry is represented by the non-shaded boxes within the clock recovery, data recovery, and digital A four-way splitter at the matched filter output is used to data router sections shown in figure 2. The circuits are delay successive outputs by QPPM slot period increments implemented with the Picologic family of GaAs logic from (0, r„ 2r„a nd 37-J. These delay lines are amplitude TriQuint Semiconductor (formerly GigaBit Logic). Figure equalized to compensate for unequal insertion losses. 8 shows a typical digital prototype board. The leadless IC Each delay line output is further split three ways, packages along with surface-mount components are producing twelve signals. The twelve signals are fed into mounted on special four layer prototype boards that six comparators to produce six ECL-level output signals for accommodate eight Picologic IC's and eight 0.4" wide 24- the QPPM decoder circuitry. The six outputs of the pin components such as ECL integrated circuits. Picologic maximum likelihood detector represent the six is compatible with the 100K ECL family using similar logic combinations of comparing the energies of the slots two at levels (-0.7 volt logic high and -1.8 volt logic low). Typical a time. Each six-way comparison is latched once per slot propagation delay times are on the order of 400-ps. On- clock period precisely when the matched filter output is at board signal interconnections between chip sites are made using semi-rigid micro coaxial cable, and inter-board The counter limit of 14 is a compromise between hardware signals use RG-174/U coaxial cable via SMA connectors. constraints and the probability of timing error as predicted All signals are terminated to -2 volts through 50 ohm by a computer model simulation. The arbitration rationale surface-mount resistors. Extreme care had to be taken in recognizes that an absence of any slot clock shift is the the design and layout to account for signal propagation most probable occurrence, and one clock shift is more times due to delays internal to the IC's and the probable than two over a given test period. Once symbol interconnect cables (50-ps per centimeter). These delays clock timing is established, the recovery circuit can be become very significant at 650-MHz, where the clock disabled until needed (for example, if major slot clock period is only 1,538 ps. References 1 and 2 describe the timing errors are detected). This scheme relies on varying hardware implementation in greater detail. source data that produces a distribution of "ones" and "zeros", resulting in approximately the same probability of occurrence of the four possible QPPM symbols. A cycle slip in the slot clock recovery will cause a shift in the r _- symbol clock, resulting in invalid symbol timing until the Now :^ symbol clock recovery circuit re-establishes the correct timing. Once generated, both slot and symbol clocks are buffered and distributed to various components of the receiver electronics. The 162.5-MHz symbol clock is used to latch the six maximum likelihood comparitor outputs for both channels at the proper sampling instant. Each latched set can then be decoded into the two binary data bits represented by the recovered QPPM symbol. These two channels of two-bit binary signals are the outputs of the data recovery portion of the receiver. Figure 8.--Typical digital circuit board. The binary data channels enter the digital data router to be de-interleaved if required, combined, and converted to As previously indicated in the analog circuits section, a serial data. De-interleaving is necessary if the transmitter' simple threshold comparitor in the BCP bit synchronizer is configured to interleave the data. The purpose of module provides a first order approximation of the QPPM interleaving is to infer the bit error rate (BER) of signals waveform at ECL logic levels, suitable for the symbol clock on one optical channel that are not pseudo random bit recovery circuit. The function of this circuit is to sequence (PRBS) data (such as video) from the BER determine where to partition the 1's and 0's of the measured on the channel carrying PRBS data. The recovered data stream into groups of valid four-bit QPPM assumption is that the interleaved non-PRBS data symbols. Specifically, it assigns the correct one of the four undergoes the same path degradations and interference as possible phases to the 162.5-MHz symbol clock. A the PRBS data. In this way a quantitative estimation can "valid/invalid" test is applied using combinational logic to be made on the non-PRBS transmission and compared to the binary waveform over a sliding window of the last four a qualitative evaluation. De-interleaving is accomplished received time slots. To be valid, a QPPM symbol must by swapping the low-order bits of the output buses. contain only a single logic "one" and three logic "zeros". Each time an invalid symbol is detected, one of four The two-bit signals from each channel are next combined counters corresponding to that specific symbol timing is into single 325-Mbps data streams in the channel data incremented. When any one of the counters reaches a multiplexers. Since the system uses no frames, unique limit (14 is used in the prototype), the other three are words, nor headers, there is no direct way to discern one surveyed to determine if one and only one of them has channel from the other if they were once interleaved. detected no invalid QPPM symbols. If so, the symbol However, this two-way ambiguity can be resolved indirectly clock is set to the phase represented by the counter by monitoring the BER measurement. The channel registering zero. If two or more counters show that no carrying PRBS data should exhibit a BER several orders invalid symbols were detected, arbitration is imposed with of magnitude below 0.5, while the non-PRBS channel's the following priorities: (1) keep the present phase, (2) BER will be very close to 0.5. Once channel ambiguity is shift the phase by +900, (3) shift by -900, and (4) shift by resolved, the process need not be repeated as long as the 1800. At this point, the counters are reset and the process data transmission is uninterrupted. begins anew, regardless of whether or not a symbol clock adjustment was made. The final process of digital data routing is for the sink data multiplexer to combine the two binary data channels into a single 650-Mbps data stream or keep the two 325-Mbps data streams separate, depending on the data sinks in the particular experiment. All three outputs (650-Mbps data and two channels of 325-Mbps data) are available on SMA connectors as complimentary pairs. In addition, all are accompanied by an appropriate clock and its compliment. Figure 9 shows the digital electronics chassis. To minimize board-to-board interconnection cable lengths, some analog circuit boards are included. Testing and Results The receiver was tested using the fully integrated Hi-LITE system, including the QPPM transmitter with laser, special test equipment (optical and rf analog), the QPPM receiver with an APD and preamplifier, data sources and sinks, and a control and monitoring computer. Figure 10 shows a block diagram of the system test configuration. Link degradations in the optical path between the QPPM transmitter and receiver were simulated by both analog and optical STE. Preliminary testing and system debugging was performed using the analog STE consisting of an additive white Gaussian noise (AWGN) generator, an rf mixer, filters, and attenuators. Figure 11 shows a photo of the analog STE chassis. Once the electronic Figure 9.--Digital electronics chassis. components of the system proved to work satisfactorily, testing through the optical STE with a laser and APD commenced. SPECIAL TEST EQUIPMENT ------- f— DATA SOURCES I OPT/CAL STE ^ DATA SINKS _______ Ila+yaxdw+xd Gower I I-------I I I I Met" I I I BER test leo lransmitler Imr TRAONSPPMMIT TER :: Lase ..A... ..I^i .. VDNaeerniuasabtalyel :.......: - -.. ....^iI . .A.. . APD: REOCPEPIVME R W.,W^, 1 I Bece vert I I era ^^ g I Filer Beam : I ^ B m.r I Y'^ I 1 ^ spflter ^ I Ydeo I Cam I 1-------------J I Mf«ft« I I I -------------- I I I VCR I I ANALOG STE I I I o d e.o dmr-VW I VCR I I I AEB I a b `" I A&B I o l I_ -I ---2 -I--- ----"I ^ I i atte waters I 2 1 smcee I `-------II------ COMPUTER CONTROL AND MONITOR BUS Figure 10.--System test configuration block diagram. 7 A camera and video cassette recorder (VCR) provide live or recorded studio-quality video data at 325-Mbps through a custom digital interface' to be displayed by a video monitor or recorded on a VCR. For quantitative ^ a performance measurements, a commercial BER test set transmitter and receiver pair provide pseudorandom bit sequences up to 2'3-1 bits in length. A 386SX personal computer is used for automated testing. It interfaces to the system hardware over digital and analog control lines and to the commercial equipment via an IEEE-488 general purpose interface bus. A typical test involves incremental rotation of the neutral density filter using its stepper motor controller to simulate specific signal-to-noise power conditions, taking optical power and BER measurements, and storing the data on disk. The computer has a graphical user interface enabling automated or manual system testing and configuring. Figure 13 shows a typical computer control screen. tliiitil. Ssa^usnis ^Itlt::!!cptlsl:Iaii : Stoce^:piiu! Y^iir:ilual^sfs.:^esl< ..... B — _ iBggt ^ f1'Ff,gigg'gBgg^c^gDggggSggg&ggggdpp3ggL 1AC1U^^ggp^p ^e"-^.v yF.v tlrOOC 6^.r^Me' Source HOOe((^^^^'' ............... hLS I[OIR ago ^C ` rov. I^ u^ el lteJC^ t.urlYelM _ d.wr p J K W l i l a l o.. M^ ^ J ou"^ o^ ^ ®n)Ilfn]I Cluk I[ICk 1 W IY^J.gWly PClO4^40n ibl tbtY lo(Y MI^YO^ Wid10011 Figure 11.--Analog special test equipment chassis .. r,...:.4.^ tV44u1 4x[ w .« ... The optical STE includes a variable neutral-density optical ^^ ICI ^^ oe4«: filter, followed by a beam splitter which feeds both an Fb9.20n11J '^ ornoY4m pu.r optical power meter for power measurements, and the Totr Pduef Ia0m1 dry} a1ls^nllm W en APD. Figure 12 shows a photograph of the optical link Uwp4 sn WJ4un ';;^ components, including: laser, variable neutral-density filter, fixed attenuation filters, mirrors, beam splitter, power Figure 13.--Computer control and monitor screen. meter sensor, focusing lens, and the APD. In the analog STE test configuration, AWGN is controlled by a variable attenuator and imposed on the signal by means of an rf mixer. Test results for the QPPM system using analog link simulation are very close to theoretical predictions. Figure 14 shows plots of the measured BER versus Eb/No as compared to the theoretical limit for orthogonal signaling'. The receiver performance is Tess than 1-dB from optimum for high BER and within 2-dB for lower BER. Causes of this slight degradation from optimum include: non-ideal pulse shapes coming from the QPPM transmitter, slot clock recovery jitter, and other circuit implementation losses in the receiver hardware. Degraded performance due to slot clock recovery jitter can be clearly seen in Figure 14, where the measured BER versus Eb/No data is also compared to performance with a hardwired clock directly from the transmitter. The BCP Figure 12.--Optical special test equipment. module used for slot clock recovery is a commercial unit designed for fiber optic applications, not intended for use below about 21-dB Eb/No. Not surprisingly, it starts slipping clock cycles at an Eb/Na of around 12-dB. When phbotiot ns _ Yl PaveTsym a slot clock cycle slip occurs the symbol timing becomes 2hf(1+31Re) incorrect and remains so until the receiver re-acquires proper timing. The slot clock recovery performance was improved by cascading the BCP module with a clock where r) is 0.77, the quantum efficiency of the APD recovery circuit from Hewlett-Packard (HDMP-2501). (dimensionless), P_ is the average optical power in watts, Adding some custom signal conditioning circuitry enabled T,Y. is the symbol period for 162.5-Megasymbols/second, the system to operate down to nearly 8-dB Eb/No with hf is the photon energy at the laser frequency f (h is much improved performance. A flight system receiver Plank's constant, 6.626 x 10" J-s, f = ca, where c = 3 x would require a more stable phased locked loop, custom 10' m/s and A = 830-nm), and R, is the laser extinction designed to operate at low E,/N. levels. ratio factor (dimensionless) estimated at 20. The (1 + 3/R.) term comes from the finite extinction ratio of a BER vs EblNo 1e-1 QPPM modulated laser. The 3 "off' slots per QPPM symbol actually contribute to some of the measured 1e-2 .—^ experimental average power. The factor of 2 in the denominator o--a ha raw i red c I k accounts for one QPPM symbol representing two binary bits. le-3 theoretical le-4 BER vs Photons/Bit to-1 le-5 w to-2 •^ experimental m le 6 theoretical to-3 le-7 a to-4 cc le-8 0 1e-5 to-9 5 6 7 8 9 10 11 12 13 14 15 to-6 EbINo (dB) to-7 Figure 14.--Analog STE configuration results comparing theory to experimental data with and without hardwired 1e-2 slot clocks. to-9 100 400 700 1000 Test results using the optical STE are shown in Figure 15. Photons/Bit A plot of BER versus average received photons per bit is compared to the theoretical optimum for the APD'. Figure 15---Optical STE configuration results comparing Optimizing the APD bias set point for the lowest BER theory to experimental data. fixed the APD gain at 100, though a gain of 200 is theoretically optimal for the APD alone'. The theoretical curve does not take into account the implementation loss The high number of photons per bit in figure 15 is due of the receiver electronics, as shown in figure 14. primarily to the relatively low sensitivity of the Newport Experimental data shown are from hardwired clock tests, APD. With the state-of-the-art hybrid APD and allowing operation at higher BER without experiencing slot preamplifier developed by EG&G, the receiver is expected clock cycle slips due to poor clock recovery circuit to operate below 100 photons per bit at 10' BER'. Also, performance at low photon per bit levels. As discussed a laser with a bandwidth of only 500-MHz was used previously under analog STE testing, slot clock recovery instead of the required 650-MHz. This causes additional circuit cycle slips begin at around 500 photons per bit, and degradation from the theoretical curve. The lower laser performance is degraded from hardwired clock operation bandwidth increases the pulse rise and fall times, degrading by about 40 photons per bit. The photons per bit values performance through increased intersymbol interference. were calculated from the received average optical power Finally, implementation loss in the electronics, as measured measurement using the following equation': with the analog STE, also contributes to the deviation from 9