Microcontrollers, Second Edition: From Assembly Language to C Using the PIC24 Family Bryan A. Jones Robert B. Reese J.W. Bruce Cengage Learning PTR Australia, Brazil, Japan, Korea, Mexico, Singapore, Spain, United Kingdom, United States Microcontrollers, Second Edition: © 2015 Cengage Learning PTR. From Assembly Language to C CENGAGE and CENGAGE LEARNING are registered trademarks of Cengage Using the PIC24 Family Learning, Inc., within the United States and certain other jurisdictions. Bryan A. Jones, Robert B. Reese, and J.W. Bruce ALL RIGHTS RESERVED. No part of this work covered by the copyright herein may be reproduced, transmitted, stored, or used in any form or by any means graphic, electronic, or mechanical, including but not limited to Publisher and General Manager, photocopying, recording, scanning, digitizing, taping, Web distribution, Cengage Learning PTR: information networks, or information storage and retrieval systems, except Stacy L. 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Proofreader: All images © Cengage Learning unless otherwise noted. Kelly Talbot Editing Services Library of Congress Control Number: 2014945697 Indexer: ISBN-13: 978-1-305-07655-6 Kelly Talbot Editing Services ISBN-10: 1-305-07655-9 eISBN-10: 1-305-07656-7 Cengage Learning PTR 20 Channel Center Street Boston, MA 02210 USA Cengage Learning is a leading provider of customized learning solutions with office locations around the globe, including Singapore, the United Kingdom, Australia, Mexico, Brazil, and Japan. Locate your local office at: international.cengage.com/region. Cengage Learning products are represented in Canada by Nelson Education, Ltd. For your lifelong learning solutions, visit cengageptr.com. Printed in the United States of America Visit our corporate Web site at cengage.com. 1 2 3 4 5 6 7 16 15 14 RBR: To my wife (Donna) and sons (Bryan and Brandon)—thanks for putting up with me. BAJ: To my beloved wife and to my Lord; soli Deo gloria. JWB: To all of my teachers. Thank you. Acknowledgments The authors would like to thank the following individuals for their assistance in preparing this book: (cid:2) ECE 4723/6723 and ECE 3724 students for their patience during the development of this text and the accompanying software libraries. That includes ECE 3724 TAs Hejia Pan, Ian Turnipseed, and Ryan Nazaretian for their assistance during this transition. Ryan also served as an ECE 4723/6723 TA. (cid:2) To the members of the Microchip Academic Program team at Microchip Technology Inc. for their support in using Microchip products in a higher-education environment. iv About the Authors BRYAN A. JONES received B.S.E.E. and M.S. degrees in electrical engineering from Rice University, Houston, TX, in 1995 and 2002, respectively, and a Ph.D. in electrical engineering from Clemson University, Clemson, SC, in 2005. From 1996 to 2000, he was a Hardware Design Engineer for Compaq, specializing in board layout for high-availability RAID controllers. Since 2005, he has served in the Department of Electrical and Computer Engineering at Mississippi State University, Mississippi State, where he is an Associate Professor. His research interests include literate pro- gramming, engineering education, embeddedsystems, and visual guidance for micro air vehicles. ROBERT B. REESE received a B.S. from Louisiana Tech University, Ruston, in 1979 and M.S. and Ph.D. degrees from Texas A&M University, College Station, in 1982 and 1985, respectively, all in electrical engineering. He served as a member of the technical staff of the Microelectronics and Computer Technology Corporation (MCC), Austin, TX, from 1985 to 1988. Since 1988, he has been with the Department of Electrical and Computer Engineering at Mississippi State University, Mississippi State, where he is an Associate Professor. Courses that he teaches include Microprocessors, VLSI systems, Digital System Design, and Senior Design. His research interests include self-timed digital systems and computer architecture. J.W. BRUCEreceived a B.S.E. from the University of Alabama in Huntsville in 1991, an M.S.E.E. from theGeorgia Institute of Technology in 1993, and a Ph.D. from the University of Nevada Las Vegas in 2000, allin electrical engineering. Dr. Bruce has served as a member of the technical staff at the Mevatec Corporation, providing engineering support to the Marshall Space Flight Center Microgravity Research Program. He also worked in the 3D Workstation Graphics Group at the Integraph Corporation, designing the world’s first OpenGL graphics accelerator for the Windows operating system. Since 2000, Dr. Bruce has served in the Department of Electrical and Computer Engineering at Mississippi State University. Dr. Bruce has contributed to the research areas of data converter architecture design and embedded systems design. He has published more than 35 tech- nical publications, several book chapters, and one book. v This page intentionally left blank Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv PART I DIGITAL LOGIC REVIEW AND COMPUTER ARCHITECTURE FUNDAMENTALS . . .1 Chapter 1 Number System and Digital Logic Review . . . . . . . . . . . . . . .3 Learning Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Using Binary Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Unsigned Number Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Hex to Binary, Binary to Hex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Combinational Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Combinational Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 The Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 The Adder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 The Incrementer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 The Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Understanding Sequential Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 The Clock Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 The D Flip-Flop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Sequential Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 The Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 The Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 The Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Encoding Character Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Review Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 vii viii Table of Contents Chapter 2 The Stored Program Machine . . . . . . . . . . . . . . . . . . . . . . . .33 Learning Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Problem Solving the Digital Way . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Finite State Machine Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Finite State Machine Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 37 A Stored Program Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Instruction Set Design and Assembly Language . . . . . . . . . . . . . . . . . . 40 Hardware Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Modern Computers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Review Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 PART II PIC24 μC ASSEMBLY LANGUAGE PROGRAMMING . . . . . . . . . . . . . . . . .51 Chapter 3 Introduction to the PIC24 Microcontroller Family . . . . . . . .53 Learning Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Introduction to Microprocessors and Microcontrollers . . . . . . . . . . . . . . . .54 The PIC24 Microcontroller Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Program Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Data Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Arrangement of Multibyte Values in Data Memory. . . . . . . . . . . . . . . 60 Data Transfer Instructions and Addressing Modes . . . . . . . . . . . . . . . . . . .62 Register Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 File Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 WREG—The Default Working Register . . . . . . . . . . . . . . . . . . . . . . . . . 67 Immediate Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Instruction Set Regularity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Basic Arithmetic and Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .74 Three-Operand Addition/Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Two-Operand Addition/Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Increment, Decrement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Program Control: goto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 A PIC24 Assembly Language Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 C-to-PIC24 Assembly Language. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 16-Bit (Word) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 The Clock and Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Review Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Table of Contents ix Chapter 4 Unsigned 8/16-Bit Arithmetic, Logical, and Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . .95 Learning Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Bitwise Logical Operations, Bit Operations . . . . . . . . . . . . . . . . . . . . . . . . .96 Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Using Shift and Rotate Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Using Mixed 8-Bit/16-Bit Operations, Compound Operations . . . . . . . . .105 Working Register Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 LSB and MSB Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Conditional Execution Using Bit Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Unsigned Conditional Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Conditional Tests in C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Zero, Non-Zero Conditional Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Bit Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Equality, Inequality Conditional Tests. . . . . . . . . . . . . . . . . . . . . . . . . . 116 Conditional Tests for >=, >, <, and <= . . . . . . . . . . . . . . . . . . . . . . . . . 116 Comparison and Unsigned Branch Instructions. . . . . . . . . . . . . . . . . . 118 Complex Conditional Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Review Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Chapter 5 Extended Precision and Signed Data Operations . . . . . . .133 Learning Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Extended Precision Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 32-Bit Assignment Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 32-Bit Bitwise Logical Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 32-Bit Addition/Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 32-Bit Logical Shift Right/Shift Left Operations. . . . . . . . . . . . . . . . . . 141 Zero, Non-Zero Conditional Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Equality, Inequality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Comparisons of >, > =, <, and < = on Unsigned 32-Bit Operands. . . . 145 64-Bit Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Signed Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 Signed Magnitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 One’s Complement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Two’s Complement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Sign Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Two’s Complement Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Operations on Signed Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Shift Operations on Signed Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Comparisons of >, >=, <, and < = on Signed Operands. . . . . . . . . . . . 157