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Microcomputers And Microprocessors. The 8080, 8085 and Z-80 Programming, Interfacing and Troubleshooting PDF

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SECOND EDITION AND_ MICROPROCESSORS THE 8080,8085, AND Z-80 PROGRAMMING, INTERFACING, AND TROUBLESHOOTING JOHN UFFENBECK OOLf . lb U l'‘: COVENTRY UNIVERSITY LANCHESTER LIBRARY 800 LANCHESTER LIB RAF v\ Coventry U Much Park Street 7HF ) MICROCOMPUTERS AND MICROPROCESSORS The 8080, 8085, and Z-80 Programming, Interfacing, and Troubleshooting Second Edition John Uffenbeck Prentice Hall, Inc. Englewood Cliffs, New Jersey 07632 Library of Congress Cataloging in Publication Data Uffenbeck, John E. Microcomputers and microprocessors : the 8080, 8085, and Z-80 : programming, interfacing, and troubleshooting / John Uffenbeck. — 2nd ed. p. cm. Includes index. ISBN 0-13-584061-9 1. Microcomputers. 2. Intel 8080 (Microprocessor) 3. Intel 8085 (Microprocessor) 4. Zilog Z-80 (Microprocessor) I. Title. QA76.5.U35 1991 004. 16—dc20 90-36041 CIP Editorial/production supervision: Tally Morgan, Wordcrafters Editorial Services, Inc. Cover design: Butler/Udell Design Manufacturing buyer: Ed O’Dougherty © 1991, 1985, by Prentice-Hall, Inc. A Division of Simon & Schuster Englewood Cliffs, New Jersey 07632 All rights reserved. No part of this book may be reproduced, in any form or by any means, without permission in writing from the publisher. Printed in the United States of America 10 9 8 7 6 5 ISBN D-lB-SflMQbl-T Prentice-Hall International (UK) Limited, London Prentice-Hall of Australia Pty. Limited, Sydney Prentice-Hall Canada Inc., Toronto Prentice-Hall Hispanoamericana, S.A., Mexico Prentice-Hall of India Private Limited, New Delhi Prentice-Hall of Japan, Inc., Tokyo Simon & Schuster Asia Pte. Ltd., Singapore Editora Prentice-Hall do Brasil, Ltda., Rio de Janeiro University Hnvpntrv Contents PREFACE 1 INTRODUCTION TO THE MICROPROCESSOR 1.1 Digital Computers: Some Basics 2 The stored program computer 2 Fetch and execute 4 The three-bus architecture 4 Computer programming 5 1.2 Computer Codes 5 Bits and bytes 6 Binary, decimal, and hexadecimal numbers 7 Codes 10 1.3 Computer Languages 12 Machine and assembly language programming 12 High-level languages 14 1.4 Implementing the Three-Bus Architecture in Hardware 16 Digital signals 16 Defining the three buses 19 1.5 The CPU as a Complex Timer 21 Machine cycle timing diagrams 21 Instruction timing 23 Processor timing 23 Chapter Summary 26 Lab Projects 27 Questions and Problems 28 Key Concept Answers 31 2 INTRODUCING THE 8080, 8085, AND Z-80 MICROPROCESSORS 2.1 Constructing the CPU Module 32 The CPU module 33 2.2 CPU Modules for the 8080, 8085, and Z-80 Microprocessors 36 The 8080 CPU module 36 The 8085 CPU module 42 The Z-80 CPU module 46 2.3 Programming Models for the 8080, 8085, and Z-80 Microprocessors 51 A programming model for the 8080 51 The 8080 flag register 52 A programming model for the 8085 55 A programming model for the Z-80 55 The Z-80 flag register 55 2.4 Introducing the Instruction Sets 57 Instruction types 57 2.5 Addressing Modes 66 68 2.6 Putting It All Together: A Programming Example Chapter Summary 70 Lab Projects 71 Questions and Problems 72 Key Concept Answers 76 3 PROGRAMMING THE MICROPROCESSOR 3.1 Microprocessor Programming Examples 79 Program 1: 8080185 8-bit addition 79 Program 2: Z-80 8-bit addition 81 Program 3: 32-bit binary addition 84 Program 4: 32-bit decimal addition 86 Program 5: 8-bit multiplication 89 Program 6: BCD-to-binary conversion 93 Program 7: filling a block of memory 98 Program 8: square-wave generator 102 Program 9: serial communications test program 103 Program 10: hex dump 105 Program 11: 1-bit I/O port 110 Program 12: frequency counter 112 Contents Program 13: the game of nim 116 Program 14: computer music 117 3.2 Operating Systems 127 Some common operating systems 128 Features of CPIM 128 A'sample session with CPIM 130 Linking programs to CPIM 135 Chapter Summary 138 Lab Projects 139 Questions and Problems 141 Key Concept Answers 143 / 4 BUILDING THE MICROCOMPUTER, PART 1: THE BUSES 145 4.1 Generating the System Clock 146 The 8080 clock 148 The 8085 clock 148 The Z-80 clock 150 4.2 Resetting the Microprocessor 152 Starting up a “new” computer 152 Reset circuits for the 8080, 8085, and Z-80 153 4.3 Electrical Characteristics of a Bus 154 Noise immunity 154 Bus loading 156 Reflections 157 4.4 Bus Buffering Techniques 160 Type 1 bus 160 Tri-state buffers with hysteresis 164 Type 2 bus 164 Type 3 bus 167 4.5 CPU Modules for the 8080, 8085, and Z-80 172 The 8080 CPU module 172 The 8085 CPU module 174 The Z-80 CPU module 174 Summary 177 4.6 Single-Stepping the Microprocessor 177 Single-stepping the 8080 179 Single-stepping the 8085 181 Single-stepping the Z-80 182 4.7 A Power-On-Jump Circuit for the Z-80 183 Chapter Summary 185 Lab Projects 185 Questions and Problems 187 Key Concept Answers 191 Contents v 5 BUILDING THE MICROCOMPUTER, PART 2: ADDING MEMORY 5.1 Memory Hierarchies 193 5.2 The Microprocessor Defines the Memory Timing 195 Memory-read-cycle timing 196 Memory-write-cycle timing 197 Memory interfacing requirements 199 Interfacing slow memory 199 5.3 Choosing Memory 201 ROM applications 202 RAM applications 202 The memory map 202 5.4 RAM and ROM Technologies 204 Mask-programmable ROMs 204 Field-programmable ROMs 204 Static and dynamic RAMs 214 RAM organization 216 The universal site 217 5.5 Interfacing Static RAM and ROM to the Microprocessor 219 Interfacing the 2764 8K-byte EPROM 220 Interfacing the 2167 16K static RAM 226 Interfacing a RAM/ROM module 229 5.6 Interfacing Dynamic RAM to the Microprocessor 236 Timing diagrams for dynamic RAM 236 Refresh 238 The 8203 DRAM controller 240 The Z-80 as a refresh controller 244 5.7 Conclusion 244 Chapter Summary 245 Lab Projects 246 Questions and Problems 248 Key Concept Answers 254 6 BUILDING THE MICROCOMPUTER, PART 3: INPUT/OUTPUT 6.1 Parallel I/O: Interfacing to a Type 3 Bus 257 HO machine cycles and timing 257 Designing an 8-bit input port 260 Designing an 8-bit output port 262 Applications for the device select pulse 265 6.2 Memory-Mapped I/O 265 Designing an 8-bit memory-mapped input port 268 Designing a digital lock 268 6.3 Handshaking Logic 274 Busy, ready, and acknowledge flags 274 6.4 Programmed I/O 275 Polling 276 Contents

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