MEHRAN MURTAIZ AMIN HIGH SPEED MONOLITHIC LEVEL SHIFTER FOR LC TYPE DCDC CONVERTER IN 45NM CMOS TECHNOLOGY. Master of Science Thesis Supervisor: Professor Nikolay T. Tchamov, Ph. D Examiner: Prof. Nikolay T. Tchamov and Jani Järvenhaara Examiners and subjects were approved in the Faculty of Computing and Electrical Engineering Council meeting on 13- August-2014 ABSTRACT TAMPERE UNIVERSITY OF TECHNOLOGY Master’s Degree Programme in Electrical Engineering Mehran Murtaiz Amin: High Speed Monolithic Level Shifter for LC Type DCDC Converter in 45nm CMOS Technology. Masters of Science Thesis, 57 pages February 2015 Major: Electrical Engineering Supervisor: Prof. Nikolay T. Tchamov, Ph. D Examiners: Prof. Nikolay T. Tchamov and Jani Järvenhaara Keywords: DC-DC converter, Level shifter, CMOS, 45nm Level shifter is an important building block in the power management system. In the DC-DC buck converter, requires a control signal with very low rise and fall time. Level shifters are used to convert low voltage signal to high voltage signal for the high side PMOS transistor of the power stage and allows increasing the efficiency of the DCDC buck converter with low rise and fall time. This thesis presents High voltage tolerant level shifter using differentially switched cascode transistor topology in cascade structure. This high voltage tolerant level shifter is providing high voltage control signal to the power stage of the step down dc-dc converter. Output signal of the level shifter has an offset of 5VDD of the nominal supply voltage at high frequency with a very low power loss of 1.84mW where each VDD is 1V. P-Driver and N-Driver provides dead time controlled signal for the power stage PMOS and NMOS transistor. The dead time for the high to low side is 157ps and low to high side is 115ps. The layout of single stage level shifter is presented which consumes a silicon area of 83.54×121.86 [μm×μm] and layout of the all three stages consumes 262.82×124.66 [μm×μm] of silicon area. The converter is designed in standard 1V, Cadence 45nm Generic Process Design Kit (GPDK). The switching frequency is 52MHz. The converter operates with 6V input voltage and provides 1.25V constant output voltage. When the input power is 200mW, the extracted simulation gives a peak conversion efficiency of 79.65% with 200mA output current. All the result and the efficiency calculation are presented with PCB and package parasitic for real component. I PREFACE The research work presented in this thesis was done at the RFIC Laboratory, Department of Electronics and Communications Engineering, Tampere University of Technology (TUT). It is the continuation of a project with our industry partner Ericson, who financially supported the research developments. During the 1-year period, I have received a lot of help from my supervisor and colleagues in our group. Foremost, I would like to thank Prof. Nikolay T. Tchamov for providing me the great opportunity to work in his research group. I also would like to thank my direct consultant Jani Järvenhaara for their unconditional help. Meanwhile, I want to thank all other team members of RFIC Laboratory for the excellent work environment we have created together. Last but not least, I would like to thank my parents for their continuous support and inspiration, which have been the main source of motivation during my M.Sc. study. Tampere, February 2015 Mehran Murtaiz Amin Opiskelankatu 4 D 638 33720 Tampere FINLAND Tel. +358451401978 II LIST OF FIGURES Figure 1-1: Battery operated application with DCDC converter .........................................1 Figure 1-2: A simple model of linear DC–DC Converter....................................................2 Figure 1-3: Schematic representation of a switched-capacitor DC–DC converter (V = out 2×V ) ...................................................................................................................................3 in Figure 1-4: Cascode Structured Standard CMOS Devices ..................................................9 Figure 2-1: Block Diagram of the DCDC Buck Converter. ..............................................11 Figure 2-2: Schematic Diagram of the Schmitt Trigger ....................................................12 Figure 2-3: Input output characteristic of the comparator .................................................12 Figure 2-4: NOS circuit symbol.........................................................................................13 Figure 2-5: Circuit Schematic of NOS...............................................................................13 Figure 2-6: Output signal of the NOS circuit.....................................................................14 Figure 2-7: Reference voltages for the converter...............................................................15 Figure 2-8: P-Driver Circuit Schematic .............................................................................17 Figure 2-9: N-Drive Circuit Schematic..............................................................................17 Figure 2-10: Output Signal of P-Driver and N-Driver.......................................................18 Figure 2-11: Circuit diagram of the power stage ...............................................................19 Figure 2-12: Output Filter of the Buck Converter .............................................................20 Figure 2-13: Simulated steady-state waveforms of the DCDC Converter circuit Output signal of the power stage at f =52MHz, V =6V, V =1.25V, I =200mA....................22 s BAT out out Figure 3-1: A conventional Level Shifter Circuit [15]. .....................................................23 Figure 3-2: Standard Cascode Structure Level Shifter Circuit ..........................................24 Figure 3-3: Modified Level Shifter for one VDD offset....................................................25 Figure 3-4: Modified Level Shifter Circuit with an offset of two VDD............................27 Figure 3-5: Simulation Result of the V , V and V of (a) Transistor ML1 to ML3 (b) ds gs gd Transistor ML6 to ML8 .....................................................................................................29 Figure 3-6: Node Voltages of the High Voltage Level Shifter ..........................................30 Figure 3-7: High Voltage Level Shifter with six VDD offset ...........................................31 Figure 3-8: Test Bench of HV Level Shifter .....................................................................32 Figure 3-9: High Voltage Level Shifter Input-Output Characteristic ................................32 Figure 3-10: An inverter with NMOS and PMOS transistor. The size of the PMOS transistor is 1um finger width with 10 fingers and NMOS transistor is 500nm finger width 10 fingers. ................................................................................................................35 Figure 3-11: An inverter with NMOS and PMOS transistor. Both the transistor consists 15 identical PMOS and NMOS segment, which makes an overall transistor width of 150µm for PMOS and 75µm for NMOS transistor. ..........................................................36 Figure 3-12: A MIM capacitor of 5pF capacitance with 144 multiplayer. Each unit has a width of 5.37µm and height of 5.37µm. The total area of the capacitor is 83.545µm×85.61µm...........................................................................................................37 Figure 3-13: Stack NMOS and PMOS transistor used in the high voltage level shifter with biasing transistor. .......................................................................................................38 Figure 3-14: Layout of single stage level shifter. Total height is 121.86um and width is 83.54um..............................................................................................................................39 III Figure 3-15: Layout of high voltage level shifter for all three stages. Total height is 124.66um and width is 262.84um. .....................................................................................40 Figure 4-1: Simulation test bench of the converter with PCB and Package parasitic. ......42 Figure 4-2: Simulated waveform of the DCDC Buck converter with all the PCB and Package parasitic and with real components......................................................................43 Figure 4-3: Precise Inductor Model ...................................................................................44 Figure 4-4: S-Parameter Simulation Setup for Characterizing Inductor ...........................45 Figure 4-5: Inductor Comparison with Datasheet and Simulation. ...................................46 Figure 4-6: Precise Capacitor model..................................................................................47 Figure 4-7: S-Parameter Simulation Setup for Characterizing Capacitor. ........................48 Figure 4-8: Capacitor Model C0510X6S0G104M030AC comparison with Datasheet and Simulation. .........................................................................................................................49 Figure 4-9: Capacitor Model C603X5R1E104M030BB Comparison with Datasheet and Simulation. .........................................................................................................................50 Figure 4-10: Capacitor Model C0603X7R1E101K030BA Comparison with Datasheet and Simulation. ..................................................................................................................51 Figure 4-11: Capacitor Model C0603X7R1E222K030BA Comparison with Datasheet and Simulation. ..................................................................................................................52 Figure 4-12: Power Loss Chart of the Different Blocks of the DCDC Converter.............53 IV Contents 1 Introduction...................................................................................................................1 1.1 DCDC Converter IC Types ...................................................................................2 1.2 Design Challenges of HV Circuit with Low Voltage CMOS Transistor ..............5 1.3 Breakdown Mechanisms .......................................................................................8 1.4 Cascode Structure: High Voltage CMOS Solution ...............................................9 2 LC Type DCDC Buck Converter Design ...................................................................10 2.1 Design Specification ...........................................................................................10 2.2 Switching Frequency Selection ...........................................................................10 2.3 Output Ripple ......................................................................................................10 2.4 System Architecture ............................................................................................11 2.5 Comparator ..........................................................................................................12 2.6 Non-Overlapping Switching Circuit ...................................................................13 2.7 High Voltage Level Shifter Circuit .....................................................................15 2.8 Biasing Circuit.....................................................................................................15 2.9 P-Driver and N-Driver Circuit ............................................................................16 2.10 Power Stage .....................................................................................................19 2.11 Output Filter Design ........................................................................................20 3 HV Level Shifter Design, Simulation and Layout......................................................23 3.1 Conventional Cascode Structure Level Shifter Circuit .......................................23 3.2 Standard Cascode Structure Level Shifter Circuit ..............................................24 3.3 Modified Cascode Structure Level Shifter Circuit for one VDD offset .............25 3.4 Modified Cascode Structure Level Shifter Circuit for two VDD offset .............27 3.5 High Voltage Level Shifter Circuit for five VDD offset ....................................31 3.6 Layout Design .....................................................................................................34 Layout design guidelines ...............................................................................................34 3.7 Layout design of The Level Shifter.....................................................................34 4 Measurement Setup and Results with PCB and Package Parasitic ............................41 4.1 Component Evaluation ........................................................................................44 4.2 Efficiency Calculation:........................................................................................53 5 Conclusion ..................................................................................................................55 References ..........................................................................................................................57 V ABBREVIATIONS DC-DC Direct-Current to Direct-Current CMOS Complementary Metal Oxide Semiconductor MOS Metal-Oxide-Semiconductor IC Integrated Circuit PWM Pulse Width Modulation DTLH Dead Time at Low-to-High transition DTHL Dead Time at High-to-Low transition NOS Non-overlapping switching NMOS N-type Metal Oxide Semiconductor PMOS P-type Metal Oxide Semiconductor VPCD Virtuoso Passive Component Designer LVS Layout vs. Schematic DRC Design Rule Check PCB Printed Circuit Board PFM Pulse Frequency Modulation VI 1 Introduction Portable electronic devices have developed significantly in the recent years. These devices use batteries as their power supply. Among these batteries Li-Ion battery is commonly used. Li-Ion batteries provide output voltage from 4.2V to 2.6V [1]. As the battery voltage fluctuates, these batteries cannot be used as a direct power supply for the devices. Most of these devices operate at fixed voltage level. To overcome this problem, power management unit is used between the battery output and the electronic circuit’s supply input. The fundamental purpose of Power management unit is to regulate the battery output voltage at a fixed voltage, which is appropriate for the operation of the electronics circuit. DC-DC converter is one of the major components of the Power management unit. DC-DC converter known as switching voltage regulator provides constant, smooth regulated output voltages while the input voltage and the load current is varying widely. In the portable devices different components requires fix various voltage and current level for operation. In order to ensure coherent operation of these circuits so that a stable system can be formed and maintained, high quality voltage regulation is necessary. The power distribution system from the battery for the different electronic application blocks is illustrated in Figure 1-1. A charger with transformer line isolation converts the AC line voltage to DC voltage to charge the battery. A lithium-ion battery supply unregulated voltage to the power management unit which contain a number of DCDC converters. DCDC converters generate the regulated supply voltages required by the different application block from the unregulated battery supply voltage. PMU 2.5V DC-AC 5.5V Audio Converter & Display Interface Charger DC-DC PWM Li-ion 2.5- 6V Converter RF D/A PA g/ traRnescftoifrimerer Battery DC-DC 2.5V Analo AL/DO LNA line isolation Converter 2.5V I/O Interface DC-DC 2.5V Converter Figure 1-1: Battery operated application with DCDC converter 1 1.1 DCDC Converter IC Types DCDC converter can generate a fix specified DC voltage required by the different circuit block for the system. The voltage generated from the converter must be maintained within tight voltage envelope to satisfy the guaranteed performance and functionality of the circuit. Different techniques converters can be used to achieve fix DC voltage and every technique has its own advantages and disadvantages. DCDC converter can be divided into two main topologies depending on the properties of the converter. Linear converter and switched capacitor converter are two of them. The switching converters can be buck, boost or buck-boost type converter. Buck converter provides lower output regulated voltage where boost converter provides higher regulated output voltage than the input voltage. Buck-boost converters are capable of providing both higher and lower output voltage. I. Linear Voltage Converter Linear converter also known as series-pass converter is very popular among the designers due to the simplicity and smaller area of the circuit. Efficiency of linear converter is a major concern as it takes the ration between output and input voltage. For the higher voltage conversion the ratio becomes less [3]. The operation of a simple linear converter is illustrated in Figure 1-2. In the simple linear DCDC converter V is the input power supply and V is the in out output voltage supplied to the load resistance R . The variable resistor R lowers the L var input supply voltage to output voltage. The maximum efficiency η attained from the max simple linear converter is V  OUT V (1.1) in V out I R Load var R L V o in ad Figure 1-2: A simple model of linear DC–DC Converter. 2 As shown in equation (1-1), linear DCDC converter can only provide high efficiency when the voltage difference between output and input voltage is small. For the higher voltage conversion, the voltage difference between output and input voltage becomes higher and the efficiency decreases. Therefore, the switched-mode DC-DC converter topologies emerge, where high conversion ratio is needed [4]. II. Switched Capacitor Converter Switched capacitor converter is also known as charge pump converter which can provide different DC output voltage level with different magnitude and/or an opposite polarity with respect to the input voltage. Switched capacitor type converters are widely used to in analog mixed signal circuit for the on-chip integrated circuit [3]. Capacitors are used to transfer charge from the input supply voltage to the output of the converter. This capacitor size is depended on the frequency of operation of the circuit. Higher frequency operation allows smaller valued capacitor but the losses in the capacitor prevent to achieve higher efficiency in the fully integrated Switched capacitor type DCDC converter. Figure 1-3 is an example of switched capacitor converter. S 1 V out S S 2 C1 2 ILoad R C Lo out a V S d in 1 Figure 1-3: Schematic representation of a switched-capacitor DC–DC converter (V = 2×V ) out in The circuit has two mutually switching networks S and S which is controlled by 1 2 two phase control signal. Switch S is controlled by the phase 1 control signal and switch 1 S is controlled by the phase 2 control signal. Phase 1 and phase 2 control signals are 2 non-overlapping control signal so when phase 1 switch is active, phase 2 switch is in cut off, capacitor C is charged to input supply voltage Vin. In this state, output capacitor C 1 out supplies the output current. When capacitor C is fully charged to supply voltage, phase 1 1 switch is cut off and phases 2 switches is activated, which allows output capacitor to be charged to twice of supply voltage. The output voltage in a practical switched capacitor converter will not be twice of the supply voltage because of the voltage drop across the series resistance of the MOSFET switches, which will degrade the efficiency of the converter. The disadvantage of charge-pump converter is the poor efficiency characteristics, discrete output voltages and low output current as compared to inductive type switch mode converter. Switched capacitor converter relies on periodically charging and discharging of the capacitor through the resistive switches. The power loss of this type 3