Sandeep Saini Low Power Interconnect Design Low Power Interconnect Design Sandeep Saini Low Power Interconnect Design 123 SandeepSaini TheLNMInstituteofInformationTechnology Jaipur,Rajasthan,India ISBN978-1-4614-1322-6 ISBN978-1-4614-1323-3 (eBook) DOI10.1007/978-1-4614-1323-3 LibraryofCongressControlNumber: 2014952901 SpringerNewYorkHeidelbergDordrechtLondon ©SpringerScience+BusinessMediaNewYork2015 Thisworkissubjecttocopyright.AllrightsarereservedbythePublisher,whetherthewholeorpartof thematerialisconcerned,specificallytherightsoftranslation,reprinting,reuseofillustrations,recitation, broadcasting,reproductiononmicrofilmsorinanyotherphysicalway,andtransmissionorinformation storageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilarmethodology nowknownorhereafterdeveloped. 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Printedonacid-freepaper SpringerScience+BusinessMediaLLCNewYorkispartofSpringerScience+BusinessMedia(www. springer.com) Dedicatedtomyparentsand mywifeManpreetKaur Preface Motivation Indeepsub-micron(DSM)technologies,interconnectsnolongerbehaveasresistors butmayhaveassociatedparasiticssuchascapacitanceandinductance.Withalinear increaseininterconnectlength,boththeinterconnectcapacitance(C)andintercon- nect resistance (R) increase linearly, making the RC delay increase quadratically. Withthecontinuoustrendofverylargescaleintegration(VLSI)technologyscaling and frequency increasing, interconnect delay becomes a significant bottleneck in system performance. From international technology roadmap for semiconductors (ITRS)projection,interconnectdelaycancontributetomorethan50%ofthedelay whenthefeaturesizeisbeyond180nm.Asaresult,delayoptimizationtechniques for interconnect are increasingly important for achieving timing closure of high performance designs. Although the RC delay is not a precise measure of the time necessary forasignaltopropagate throughawire,thetotalRCdelayofasection of a line may be useful as a figure of merit. In order to increase the operating speed of an integrated circuit, it is necessary to reduce the RC delay. In addition toincreasedsignalpropagationdelay,increasedpowerdissipationisanothereffect oflargeinterconnectimpedance. The total RC delay of an interconnect line can be reduced drastically with the insertion of a signal amplifier known as a repeater. In CMOS technology, the simplest form of a repeater is produced from a two transistor inverter. But buffer insertion is becoming a bulky technique for DSM technologies, requiring finding the solution with different approach. This book discusses an alternative approach to buffer insertion for the purpose of delay, power, and noise reduction in VLSI interconnectinDSMtechnology. Signals on an interconnect get highly distorted due to propagation delay and coupling effects of adjacent lines. The effect of this is shown in Fig.1 for a group of eight interconnects laid side by side at 65nm technology. This figure depicts the delayed signals on interconnects of length equal to 1mm. There are not only visiblepropagationdelaysineachsignalbutalsoquitesignificantpresenceofnoise vii viii Preface glitches due to switching signals on adjacent lines. Hence along with power and delay,noisecancellationisalsoanimportantpointtobenotedwhiledevelopingthe algorithm/techniqueforbettertransmission. Fig.1 Thewaveformforan8bitwide1mmlongbusat65nmtechnology Preface ix HowtoUtilizethisBook This book assumes the reader to be well aware of VLSI technology. One should havecoveredthebasicintroductorycourseonVLSIdesignandtechniquemethods and have fair understanding of issues in system design. The majority of this book is intended for use in senior level interconnect design. It has been discussed that interconnectsareamajorbottleneckinVLSIsystemdesign,thusmostofthechap- ters in this book are based on efficient interconnect design methodologies. These are divided into two different categories depending upon the type of application. The reader might be interested in one or both types of design methods and have a thorough study about them. The core of the first chapter is mainly written for new readers in this field. Interconnects and their basic properties and behavior are introducedinthischapter.Thismakesthefoundationfortherestofthebook.Once youarefamiliarwithdifferentpropertiesandissuesininterconnectdesign,youcan understand the rest of the chapter. In order to maintain a consistent flow through each of the chapters, all the topics are introduced first, followed by the detailed discussion about algorithms and ideas. Each topic has been well supported with adequatesimulationstoverifythetheory. SalientFeaturesoftheBook • Thisbookfocusesonlyonthedeepsub-microntechnologydevicesandintercon- nects. • ResearchorienteddiscussionsonrecenttrendsinVLSItechnology. • ProvidescoverageonlatestdesigntoolsinDSMandexamplesforbasicdesigns. • Providesdetailedsimulationresultstosupportthetheoreticaldiscussions. • Offersperspectivesonhowinterconnectsmightevolveinthefuture. ContentsataGlance Aquickviewofthetableofcontentswouldgiveanideatothereaderthatthewhole book is divided into three major parts. Part I comprises of Chaps. 1 and 2 which acts as a foundation and global introduction to the rest of the book. Chapters 3 and4arepartofPartII,whichbasicallyfocusesoninterconnectdesigntechniques based on buffer and Schmitt trigger insertion. In Chap. 2, I have introduced the concept of CMOS buffer. CMOS buffer is an integral part of delay and power efficient interconnect designs. Critical issues regarding buffer size and placement strategies are discussed in Chap. 3. Here, I have also explained the concept of optimum number of buffers for best results. In Chap. 4, an attempt has been madetoreplaceCMOSbufferwithSchmitttriggerforpowerefficientinterconnect design. This approach is proved to be better than the conventional approach and saves propagation delay as well. Part III consists of Chap. 5 which discusses