EE247 Lecture 21 ADC Converters – Comparator design • Single-stage open-loop amplifier • Cascade of open-loop amplifiers • Problem associated with DC offset – Cascaded output series cancellation – Input series cancellation – Offset cancellation through additional input pair plus offset storage capacitors • Latched comparators • Comparator examples EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 1 Summary Last Lecture ADC Converters – Sampling (continued) • Effect of clock jitter on sampling – ADC architectures and design • Serial-slope type • Successive approximation • Flash • Flash ADC sources of error – Comparator offset – Sparkle code – Meta-stability EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 2 Voltage Comparators V DD Vi+ + V (Digital Output) V out i- - Play an important role in majority of ADCs Function: Compare the instantaneous value of two analog signals & generate a digital output voltage based on the sign of the difference: If V -V > 0 (cid:198)V =“1” i+ i- out If V -V < 0 (cid:198)V =“0” i+ i- out EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 3 Voltage Comparator Architectures Comparator architectures: • High gain amplifier with differential analog input & single-ended large swing output – Output swing has to be compatible with driving digital logic circuits – Open-loop amplification(cid:198)no frequency compensation required – Precise gain not required • Latched comparators; in response to a strobe (clock edge), inputstage disabled & digital output stored in a latch till next strobe – Two options for implementation : • Latch-only comparator • Low-gain amplifier + high-sensitivity latch • Sample-data comparators – T/H input – Offset cancellation EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 4 Comparators Built with High-Gain Amplifier Amplify V (min) to V in DD (cid:198)V (min) determined by ADC in resolution Example: 12-bit ADC with: -V = 1.5V(cid:198)1LSB=0.36mV FS -V =1.8V DD (cid:198)For 1.8V output & 0.5LSB precision: 1.8V AMin= ≈10,000 v 0.18mV EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 5 Comparators 1-Single-Stage Amplification f =unity-gain frequency, f=-3dB frequency u o f fo= u Gain A ExamVple: f =10GHz & A =10,000 u V A v f =10GHz≈1MHz fu=0.1-10GHz o 10,000 1 frequency τsettling=2πf =0.16μsec f0 fu Allowa fewo τfor output to settle Assumption: Single pole amplifier 1 fMax.→ ≈1.26MHz Clock 5τ settling Too slow for majority of applications! (cid:198)Try cascade of lower gain stages to broaden frequency of operation EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 6 Comparators 2- Cascade of Open Loop Amplifiers The stages identical (cid:198)small-signal model for the cascades: One stage: EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 7 Open Loop Cascade of Amplifiers EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 8 Open Loop Cascade of Amplifiers For |A (DC)|=10,000 T Example: N=3, f =10GHz & A(0)=10000 u T f = 10GHz 21/3−1≈237MHz oN (10,000)1/3 1 τ = =0.7nsec settling 2πf o Allowa few τfor output to settle 1 fMax.→ ≈290MHz Clock 5τ settling f improved from 1.26MHz to 290MHz (cid:198)X236 max EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 9 Open Loop Cascade of Amplifiers Offset Voltage • From offset point of view: high gain/stage is preferred • Choice of # of stage (cid:198)bandwidth vs offset tradeoff Input-referred offset (cid:198) EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 10 Open Loop Cascade of Amplifiers Step Response • Assuming linear behavior (not slew limited) t EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 11 Open Loop Cascade of Amplifiers Step Response •Assuming linear behavior EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 12 Open Loop Cascade of Amplifiers Delay/(C/g ) m • Minimum total delay broad Delay/(C/g ) m function of N • Relationship between # of stages resulting in minimize delay (N ) op and gain (V /V ) approximately: out in N ≈1+log A for A<1000 opt 2 T N ≈1.2lnA for A≥1000 opt T Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ”IEEE Journal of Solid-State Circuits,vol. 23, pp. 1379 -1385, December 1988. EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 13 Offset Cancellation • In sampled-data cascade of amplifiers Vos can be cancelled (cid:198)Store on ac-coupling caps in series with amp stages • Offset associated with a specific amp can be cancelled by storing it in series with either the input or the output of that stage • Offset can be cancelled by adding a pair of auxiliary inputs to the amplifier and storing the offset on capacitors connected to the aux. inputs during offset cancellation phase Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ”IEEE Journal of Solid-State Circuits,vol. 23, pp. 1379 -1385, December 1988. EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 14 Offset Cancellation Output Series Cancellation • Amp modeled as ideal + V (input referred) os • Store offset: •S1, S4(cid:206)open •S2, S3(cid:198)closed (cid:198)V =AxV C OS Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ”IEEE Journal of Solid-State Circuits,vol. 23, pp. 1379 -1385, December 1988. EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 15 Offset Cancellation Output Series Cancellation Amplify: • S1, S4(cid:206)closed • S2, S3(cid:198)open (cid:198)V =AxV C OS Circuit requirements: • Amp not saturate during offset storage • High-impedance (C) load (cid:198)C not c discharged • C >> C to avoid attenuation c L • C >> C avoid excessive offset c switch due to charge injection EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 16 Offset Cancellation Cascaded Output Series Cancellation Note: Offset storage capacitors in series with the amplifier outputs EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 17 Offset Cancellation Cascaded Output Series Cancellation 1-S1(cid:198)open, S2,3,4,5 closed V =A xV C1 1 os1 V =A xV C2 2 os2 V =A xV C3 1 os3 EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 18 Offset Cancellation Cascaded Output Series Cancellation 2-S3(cid:198)open first • Feedthrough from S3 (cid:198)offset on X • Switch offset , ε3 induced on node X • Since S4 remains closed, offset associated with ε3(cid:198)stored on C2 V = ε X 3 V =A xV -ε C1 1 os1 3 V =A x(V + ε ) C2 2 os2 3 EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 19 Offset Cancellation Cascaded Output Series Cancellation 3-S4(cid:198)open • Feedthrough from S4 (cid:198)offset on Y ε • Switch offset , 4induces error on node Y ε • Since S5 remains closed, offset associated with 4(cid:198)stored on C3 V = ε Y 4 V =A x(V + ε ) –ε C2 2 os2 3 4 V =A x(V + ε ) C3 3 os3 4 EECS 247 Lecture 21 Nyquist Rate ADC: Comparator Design ©2007 H.K. Page 20