Available at www.ComputerScienceWeb.com JOURNAL OF SYSTEMS POWERED BY SCIENCE DIRECT® ARCHITECTURE ELSEVIER Journal of Systems Architecture 48 (2003) 453-454 www.elsevier.com/locate/sysarc Author index to volume 48 (2002-2003) Al-Ayyoub, A., see Awwad, A.M. 325-336 ElHefnawy, A.A., see Fahmy, H.M.A. 193-198 Al-Ayyoub, A., see Loucif, S. 37-47 Entrialgo, J., see Garcia, J. 221-235 Alexiou, G., see Bakalis, D. 125-135 Awwad, A.M., A. Al-Ayyoub and M. Ould- Fahmy, H.M.A. and Abu_Bakr A. ElHefnawy, Khaoua, On the topological properties of the Methods for distributed unicast in hypercubes 193-198 arrangement-star network 325-336 Garcia, D.F., see Garcia, J. 221-235 Bakalis, D., E. Kalligeros, D. Nikolos, H.T. Garcia, J., J. Entrialgo, D.F. Garcia, J.L. Diaz Vergos and G. Alexiou, On the design of low and F.J. Suarez, PET, A software monitoring power BIST for multipliers with Booth toolkit for performance analysis of parallel encoding and Wallace tree summation 125-135 embedded applications 221-235 Béchennec, J.-L., see Drach, N. 137-149 Goutis, C., see Theoharis, S. 113-124 Bezrukov, S.L., see Das, N. 311-323 Bhattacharya, B.B., see Das, N 311-323 Ha, R., see Cha, H. 353-366 Bhuyan, L.N., see Iyer, R. 59-80 Hong, S.J., see Nam, H. 237-254 Huang, T.-C. and L.-C. Shiu, Efficient commu- Cha, H., J. Kim and R. Ha, Bandwidth cons- nication sets generation for block—cyclic dis- trained smoothing for multimedia streaming tribution on distributed-memory machines 255-265 with scheduling support 353-366 Chang, L.-C., see Ton, L.-R. 1-16 Iyer, R., H.W ang and L.N. Bhuyan, Design and Chun, S.W., see Lee, J.1. 17-35 analysis of static memory management poli- Chung, C.-P., see Ton, L.-R. 1-16 cies for CC-NUMA multiprocessors Cortés, A., see Senar, M.A. 267-283 Cotroneo, D., N. Mazzocca, L. Romano and Jézwiak, L. and A. Postuta, Genetic engineering S. Russo, Building a dependable system from versus natural evolution. Genetic algorithms a legacy application with CORBA with deterministic operators 99-112 Das, N., B.B. Bhattacharya and S.L. Bezrukov, Kalligeros, E., see Bakalis, D. 125-135 Permutation routing in optical MIN with Kang, S.J., see Lee, J.1. 17-35 minimum number of stages 311-323 Ki, A., see Lee, S. 49-57 De Bosschere, K., see Eeckhout, L. 199-220 Kim, J., see Nam, H. 237-254 De Bosschere, K., see Vandierendonck, H. 429-452 Kim, J., see Cha, H. 353-366 Diaz, J.L., see Garcia, J. 221-235 Kyung, C.-M., see Lee, S. 49-57 Dobravec, T., B. Robié and J. Zerovnik, Permu- tation routing in double-loop networks: de- Lee, J.1., S.W. Chun and S.J. Kang, Virtual sign and empirical evaluation 387-402 prototyping of PLC-based embedded system Drach, N., J.-L. Béchennec and O. Temam, using object model of target and behavior Increasing hardware data prefetching perfor- model by converting RLL-to-statechart mance using the second-level cache 137-149 directly Lee, S., see Nam, H. Eeckhout, L. and K. De Bosschere, Quantifying Lee, S., A. Ki, L-C. Park and C.-M. Kyung, behavioral differences between multimedia Interface synthesis between software chip and general-purpose workloads 199-220 model and target board 1383-7621/03/$ - see front matter © 2003 Elsevier Science B.V. All rights reserved. doi:10.1016/S1383-7621(03)00047-X 454 Author index / Journal of Systems Architecture 48 (2003) 453-454 Loucif, S., M. Ould-Khaoua and A. Al-Ayyoub, Shiu, L.-C., see Huang, T.-C. 255-265 Hypermeshes: implementation and_perfor- Soudris, D., see Theoharis, S. 113-124 mance 37-47 Srikant, Y.N., see Venugopal, R. 151-173 Luque, E., see Senar, M.A. 267-283 Srikanthan, T., see Sudha, N. 337-352 Suarez, F.J., see Garcia, J. 221-235 Mailachalam, B., see Sudha, N. 337-352 Sudha, N., T. Srikanthan and B. Mailachalam, Mattavelli, M., see Ravasi, M. 403-427 A VLSI architecture for 3-D self-organizing Mazzocca, N., see Cotroneo, D. 81-98 map based color quantization and its FPGA Meribout, M. and M. Motomura, New design implementation 337-352 methodology with efficient prediction of quality metrics for logic level design towards Temam, O., see Drach, N. 137-149 dynamic reconfigurable logic 285-310 Thanailakis, A., see Theoharis, S. 113-124 Motomura, M., see Meribout, M. 285-310 Theodoridis, G., see Theoharis, S. 113-124 Theoharis, S., G. Theodoridis, D. Soudris, C. Nam, H., J. Kim, S.J. Hong and S. Lee, Secure Goutis and A. Thanailakis, A fast and checkpointing 237-254 accurate delay dependent method for switch- Nikolos, D., see Bakalis, D. 125-135 ing estimation of large combinational circuits 113-124 Ton, L.-R., L.-C. Chang and C.-P. Chung, An 325-336 Ould-Khaoua, M., see Awwad, A.M. analytical POC stack operations folding for 37-47 Ould-Khaoua, M., see Loucif, S. continuous and discontinuous Java bytecodes Tscha, Y., Scheduling length for switching Park, I.-C., see Lee, S. 49-57 element disjoint multicasting in Banyan-type Postula, A., see J6zwiak, L. 99-112 switching networks 175-191 Tsikel, R., see Weiss, S. 367-375 Ravasi, M. and M. Mattavelli, High-level algori- thmic complexity evaluation for system de- Vandierendonck, H. and K. De Bosschere, sign 403-427 Highly accurate and efficient evaluation of Ripoll, A., see Senar, M.A. 267-283 randomising set index functions 429-452 Robic, B., see Dobravec, T. 387-402 Venugopal, R. and Y.N. Srikant, Scheduling Romano, L., see Cotroneo, D. 81-98 expression trees for delayed-load architectures 151-173 Russo, S., see Cotroneo, D. 81-98 Vergos, H.T., see Bakalis, D. 125-135 Senar, M.A., A. Ripoll, A. Cortés and E. Luque, Wang, H., see Iyer, R. 59-80 Clustering and reassignment-based mapping Weiss, S. and R. Tsikel, Approximate prefix strategy for message-passing architectures 267-283 coding for system-on-a-chip programs 367-375 Sharifi, M. and B. Zolfaghari, Modeling and evaluating the time overhead induced by BER Zerovnik, J., see Dobravec, T. 387-402 in COMA multiprocessors 377-385 Zolfaghari, B., see Sharifi, M. 377-385 Available at www.ComputerScienceWeb.com JOURNAL OF SYSTEMS POWERED BY SCIENCE DIRECT® ARCHITECTURE ELSEVIER Journal of Systems Architecture 48 (2003) 455-456 www.elsevier.com/locate/sysarc Subject index to volume 48 (2002-2003) 3-D self-organizing map 337 Evaluation Adjudication 81 Evolutionary algorithms 99 Algorithm design 387 Execution-based simulation 59 Allocation 285 Expression trees 151 Arrangement network 325 Automated design problem solving 99 Fault tolerance 81, 193, 237, 377 FPGA 337 Bandwidth smoothing 353 Banyan network 175 Gate level 113 BER strategy 377 General-purpose workloads 199 Genetic algorithms Bit-permute-complement permutations 311 Genetic engineering Block—cyclic distribution 255 Booth multipliers 125 Graph partitioning Built-in self-test 125 Graphs Bus traffic 137 Heuristic algorithms Heuristic search Cache 137 Hierarchical structure Checkpointing 237 Hybrid optical MIN’s Circuit synthesis 99 Hypercube Clustering 267 Hypergraphs CMOS circuit 113 Color quantization 337 Incremental scheduling COMA 377 Input support minimization Communication cost 285 Instruction scheduling Communication sets 255 In-system verification Compilers 151 Interconnection networks Complexity analysis 403 Interrupt controller Computer aided design 113 Computer architecture , 367 Java processor Conflict misses 427 Java virtual machine CORBA 81 Cryptography 237 Legacy systems Low power design Distributed routing 193 Low power testing Distributed shared memory 377 Double-loop network 387 Mapping problem Dynamic reconfigurable logic 285 Memory hierarchy Memory management Embedded multiprocessors 221 Microprocessor data cache Embedded system 17 MP3 Emulation 49 Multi-tier architectures End-system QoS management 353 Multicasting network EPOC folding model l Multicomputers 1383-7621/03/$ - see front matter © 2003 Elsevier Science B.V. All rights reserved. doi:10.1016/S1383-7621(03)00048-1 456 Subject index | Journal of Systems Architecture 48 (2003) 455-456 Multimedia applications 199 Relay ladder logic Multimedia streaming 353 Replication Multiplexer cost 285 RISC Multistage interconnection network 311 Scheduling Nonblocking switching network 175 Scientific applications Non-local data 255 Security Null space 427 SE-disjoint routing Shared-memory multiprocessor Object code 367 Shuffle-exchange networks Off-line routing 193 Simulation Software instrumentation Parallel algorithms 325 Software monitoring tools Parallel embedded applications 221 Software/hardware partitioning Parallel processing 37 SPMD Partitioning 285 Stack operations folding Path-dependent loss 311 Star network Performance analysis 37 Statecharts Performance measurement 221 Statistical analysis Performance visualization 221 Superscalar processor Permutation admissibility System design Permutation routing System-on-a-chip Photonic crosstalk PLC Task allocation/assignment POC folding model Power estimation Unicast Prefetching Product network Vertex symmetry Virtual cut-through Randomisation Virtual prototyping Randomising set index function VLSI architecture Real-time operating system Wallace trees Real-time task scheduling Workload characterization