82078 CHMOS Single-Chip Floppy Disk Controller CONTENTS PAGE 82078 CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER ................................. 1 82078 44 PIN CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER ......................... 5 82078 64 PIN CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER ........................ 77 I Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation. Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FAST PATH trademark or products. ·Other brands and names are the property of their respective owners. Additional copies of this document or other Intel literature may be obtained from: Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 @ INTEL CORPORATION 1993 intel .. 82078 CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER • • Small Footprint and Low Height Integrated Analog Data Separator Packages - 250 Kblts/sec • - 300 Kblts/ sec Supports Standard 5.0V as Well as Low - 500 Kblts/ sec Voltage 3.3V Platforms -1 Mblts/sec - Selectable 3.3V and 5.0V -2 Mblts/sec Configuration • - 5.0V Tolerant Drive Interface Integrated Tape Drive Support • - Standard 1 Mbps/500 Kbps/ Enhanced Power Management 250 Kbps Tape Drives - Application Software Transparency - New 2 Mbps Tape Drive Mode - Programmable Powerdown • Command Perpendicular Recording Support for - Save and Restore Commands for OV 4 MB Drives Powerdown • Fully Decoded Drive Select and Motor - Auto Powerdown and Wakeup Signals Modes • - Two External Power Management Programmable Write Precompensatlon Pins Delays - Consumes No Power While in • Addresses 256 Tracks Directly, Powerdown Supports Unlimited Tracks • Programmable Internal Oscillator • 16 Byte FIFO • Floppy Drive Support Features • Single-Chip Floppy Disk Controller - Drive Specification Command Solution for Portables and Desktops - Media ID Capability Provides Media -100% PC-AT* Compatible Recognition - 100% PS/2* Compatible - Drive ID Capability Allows the User - 100% PS/2 Model 30 Compatible to Recognize the Type of Drive - Fully Compatible with Intel's 386SL - Selectable Boot Drive Microprocessor SuperSet -Standard IBM and ISO Format - Integrated Drive and Data Bus Features Buffers - Format with Write Command for • Available in 64 Pin QFP and 44 Pin QFP High Performance in Mass Floppy Package Duplication (See Package Specification Order Number 240800, Package • Integrated Host/Disk Interface Drivers Type S) The 82078 Product Family brings a set of enhanced floppy disk controllers. These include several features that allow for easy implementation in both the portable and desktop market. The current family includes a 64 pin and a 44 pin part in the smaller form factor QFP package. The 3.3V version of the 64 pin part provides an ideal solution for the rapidly emerging 3.3V platforms. It also allows for a 5.0V tolerant floppy drive interface that lets the users retain their normal 5.0V drives. Another version of the 64 pin part provides support for 2 Mbps data rate tape drives. ·Other brands and names are the property of their respective owners. September 1993 Order Number: 290468-003 intel .. 82078 Table 1-0. 64 Pin Part Versions 3.3V 5.0V 2 Mbps Data Rate 82078SL X X 82078-1 X X The 44 pin is targeted for platforms that are operated at 3.3V or 5.0V and do not require more than two drive support. The 82078-5 is designed for price sensitive 5.0V designs which do not include 4 MB drive support. Table 2-0. 44 Pin Part Versions 3.3V 5.0V 1 Mbps Data Rate 82078 X X 82078-5 X 82078-3 X X Both parts can be operated at 1 Mbps/500 Kbps/300 Kbps/250 Kbps. Additionally, one version of the 64 pin part provides 2 Mbps data rate operation specific for the new tape drives. The 82078 is fabricated with Intel's advanced CHMOS III technology. w ~0 !~ ~ a0,.: , o~ ~9 ~ :( g ~ ~ ~ x ~ (w~aJ:) ~a: Ui 48 FDSOI DACK. 47 FDMEOI DBO 46 DRVIDO VSSP 45 FDS1. 081 44 FDME1. DB2 43 DRVID1 IDENTO 42 DIR. DB3 vssp 82078 41 VCCF vcc 40 MEDIDO 39 STEP. DB4 IDENT1 38 VSS 085 37 FDS2. Dee 36 FDME2. VSS 35 HDSEL. DB7 34 WE. SEL3V. ~ ~ ~ IN/) ~ ~ tiS 81 til 1; ~33 WRDATA. ,. ~ ~ ~ ~ ~ i ~ 8 (!J ~ ffi ~ ffi m ! 0 I!: 0l: '< ~ ~:~:t oa~: 0~ a0~: I~&. 290468-1 2 I infel .. 82078 Iii 0a0 : 3a'I::t a0'I :t 0~ ~ :( ~ ~ x ~ arwn: .,. 0~ ~ N ~ ~ ~ ~ {:j ~ ~ (I; DACKI 1 33 FDSOI DBO 2 32 FDMEO' DB1 3 FDS11IPDt DB2 4 FDME1,/IDLEI DB3 DIRI VSSP 6 VCCF vce 7 STEPI DB4 8 VSS DBS 9 HDSELI DB6 10 WE' DB7 11 WRDATAI ,. ~ 0t- 1~= ~~ 3~: rr~nn (~<.) r~~:cJn: ia0~! :i 0zw~0 cZw~ 290468-2 I 3 inteL 8207844 PIN CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER • • Small Footprint and Low Height Integrated Tape Drive Support Package - Standard 1 Mbps/500 Kbps/ • 250 Kbps Tape Drives Enhanced Power Management • - Application Software Transparency Perpendicular Recording Support for - Programmable Powerdown 4 MB Drives Command • Integrated Host/Disk Interface Drivers - Save and Restore Commands for • Zero-Volt Powerdown Fully Decoded Drive Select and Motor - Auto Powerdown and Wakeup Signals Modes • Programmable Write Precompensation - Two External Power Management Delays Pins • Addresses 256 Tracks Directly, - Consumes No Power While in Supports Unlimited Tracks Powerdown • • 16 Byte FIFO Integrated Analog Data Separator • -250 Kbps Single-Chip Floppy Disk Controller -300 Kbps Solution for Portables and Desktops -500 Kbps - 100% PC/ AT* Compatible -1 Mbps - Fully Compatible with Intel386™ SL • - Integrated Drive and Data Bus Programmable Internal Oscillator Buffers • Floppy Drive Support Features • Separate 5.0V and 3.3V Versions of the - Drive Specification Command 44 Pin part are Available - Selectable Boot Drive • -Standard IBM and ISO Format Available in a 44 Pin QFP Package Features - Format with Write Command for High Performance in Mass Floppy Duplication The 82078, a 24 MHz crystal, a resistor package, and a device chip select implements a complete solution. All programmable options default to 82078 compatible values. The dual PLL data separator has better perform ance than most board level/discrete PLL implementations. The FIFO allows better system performance in multi-master (e.g., Microchannel, EISA). The 82078 maintains complete software compatibility with the 82077SLl82077A A/8272A floppy disk control lers. It contains programmable power management features while integrating all of the logic required for floppy disk control. The power management features are transparent to any application software. The 82078 is fabricated with Intel's advanced CHMOS '" technology and is also available in a 64-lead QFP package. ·Other brands and names are the property of their respective owners. December 1993 Order Number: 290474-003 5 82078 44 Pin CHMOS Single-Chip Floppy Disk Controller CONTENTS CONTENTS PAGE PAGE 1.0 INTRODUCTION ...................... 12 4.0 POWER MANAGEMENT FEATURES ............................. 21 2.0 MICROPROCESSOR INTERFACE .... 13 4.1 Power Management Scheme ....... 21 2.1 Status, Data, and Control 4.2 Oscillator Power Management ...... 21 Registers ............................ 13 4.3 Part Power Management ........... 22 2.1.1 Status Register B (SRB, EREG EN = 1) ................... 13 4.3.1 Direct Powerdown ............. 22 2.1.2 Digital Output Register 4.3.2 Auto Powerdown .............. 22 (DOR) ... , ........................ 14 4.3.3 Wake Up Modes ............... 22 2.1.3 Enhanced Tape Drive 4.3.3.1 Wake Up from DSR Register (TDR) .................... 15 Powerdown .................... 22 2.1.4 Datarate Select Register 4.3.3.2 Wake Up from Auto (DSR) ............................ 15 Powerdown .................... 22 2.1.5 Main Status Register 4.4 Register Behavior .................. 23 (MSR) ............................ 17 4.5 Pin Behavior ....................... 23 2.1.6 FIFO (DATA) .................. 17 4.5.1 System Interface Pins ......... 23 2.1.7 Digital Input Register (DIR) ..... 18 4.5.2 FDD Interface Pins ............ 24 2.2 Reset .............................. 18 2.2.1 Reset Pin ("HARDWARE") 5.0 CONTROLLER PHASES .............. 24 Reset ............................. 18 5.1 Command Phase ................... 24 2.2.2 DOR Reset vs DSR Reset 5.2 Execution Phase ................... 25 ("SOFTWARE" RESET) .......... 18 5.2.1 Non-DMA Mode, Transfers 2.3 DMA Transfers ..................... 18 from the FIFO to the Host ......... 25 3.0 DRIVE INTERFACE ................... 18 5.2.2 Non-DMA Mode, Transfers from the Host to the FI FO .......... 25 3.1 Cable Interface ..................... 18 5.2.3 DMA Mode, Transfers from 3.2 Host and FDD Interface Drivers ..... 19 the FIFO to the Host .............. 25 3.3 Data Separator ..................... 19 5.2.4 DMA Mode, Transfers from 3.3.1 Jitter Tolerance ................ 20 the Host to the FIFO .............. 25 3.3.2 Locktime (tLOCK) .............. 20 5.2.5 Data Transfer Termination ..... 26 3.3.3 Capture Range ................ 20 5.3 Result Phase ....................... 26 3.4 Write Precompensation ............. 20 6 I CONTENTS CONTENTS PAGE PAGE 6.0 COMMAND SETI DESCRIPTIONS .... 26 7.0 STATUS REGISTER ENCODING ..... 50 6.1 Data Transfer Commands .......... 38 7.1 Status Register 0 ................... 50 6.1.1 Read Data ..................... 38 7.2 Status Register 1 ................... 50 6.1.2 Read Deleted Data ............ 39 7.3 Status Register 2 ................... 51 6.1.3 Read Track .................... 39 7.4 Status Register 3 ................... 51 6.1.4 Write Data ..................... 40 8.0 COMPATIBILITY ..................... 52 6.1 .5 Write Deleted Data ............ 40 8.1 Compatibility with the FIFO ......... 52 6.1.6 Verify .......................... 40 8.2 Drive Polling ........................ 52 6.1.7 Format Track .................. 41 6.1.7.1 Format Fields ............. 42 9.0 PROGRAMMING GUIDELINES ....... 52 6.2 Scan Commands ................... 42 9.1 Command and Result Phase Handshaking ........................ 53 6.3 Control Commands ................. 43 9.2 Initialization ........................ 53 6.3.1 Read ID ....................... 43 9.3 Recalibrates and Seeks ............ 55 6.3.2 Recalibrate .................... 43 9.4 Read/Write Data Operations ....... 55 6.3.3 Drive Specification Command ........................ 43 9.5 Formatting ......................... 57 6.3.4 Seek .......................... 44 9.6 Save and Restore .................. 58 6.3.5 Sense Interrupt Status ......... 44 9.7 Verifies ............................. 59 6.3.6 Sense Drive Status ............ 45 9.8 Powerdown State and Recovery .... 59 6.3.7 Specify ........................ 45 9.8.1 Oscillator Power Management ..................... 59 6.3.8 Configure ...................... 45 9.8.2 Part Power Management ....... 59 6.3.9 Version ........................ 46 9.8.2.1 Powerdown Modes ....... 59 6.3.10 Relative Seek ................ 46 9.8.2.2 Wake Up Modes .......... 60 6.3.11 DUMPREG ................... 47 . 6.3.12 Perpendicular Mode 10.0 DESIGN APPLICATIONS ............ 60 Command ........................ 47 10.1 Operating the 82078 in a 3.3V 6.3.12.1 About Perpendicular Design ............................... 60 Recording Mode ............... 47 10.2 Selectable Boot Drive ............. 62 6.3.12.2 The Perpendicular 10.3 How to Disable the Native Floppy Mode Command ............... 47 Contoller on the Motherboard ........ 63 6.3.13 Powerdown Mode 10.4 Replacing the 82077SL with a Command ........................ 48 82078 in a 5.0V design: .............. 63 6.3.14 Part ID Command ............ 48 11.0 D.C. SPECIFICATIONS .............. 66 6.3.15 Option Command ............ 48 11.1 Absolute Maximum Ratings ........ 66 6.3.16 Save Command .............. 48 11.2 D.C. Characteristics ............... 66 6.3.17 Restore Command ........... 48 11.3 Oscillator ......................... 67 6.3.18 Format and Write Command ........................ 49 12.0 A.C. SPECIFICATIONS .............. 68 6.3.19 Lock ......................... 49 12.1 Package Outline for the 44-Pin QFP Part ............................ 74 13.0 REVISION HISTORY .. " ............ 75 I 7