IBM PowerPC 970 (a.k.a. G5) Ref 1 David Benham and Yu-Chung Chen UIC – Department of Computer Science CS 466 PPC 970FX overview 64-bit RISC ● 58 million transistors ● 512 KB of L2 cache and 96KB of L1 cache ● 90um process with a die size of 65 sq. mm ● Native 32 bit compatibility ● Maximum clock speed of 2.7 Ghz ● SIMD instruction set (Altivec) ● 42 watts @ 1.8 Ghz (1.3 volts) ● Peak data bandwidth of 6.4 GB per second ● A picture is worth a 2^10 words (approx.) Ref 2 A little history PowerPC processor line is a product of the AIM ● alliance formed in 1991. (Apple, IBM, and Motorola) PPC 601 (G1) - 1993 ● PPC 603 (G2) - 1995 ● PPC 750 (G3) - 1997 ● PPC 7400 (G4) - 1999 ● PPC 970 (G5) - 2002 ● AIM alliance dissolved in 2005 ● Processor Ref 3 Ref 3 Core details 16(int)-25(vector) stage pipeline ● Large number of 'in flight' instructions (various ● stages of execution) - theoretical limit of 215 instructions 512 KB L2 cache ● 96 KB L1 cache ● 64 KB I-Cache – 32 KB D-Cache – Core details continued 10 execution units ● – 2 load/store operations – 2 fixed-point register-register operations 2 floating-point operations – 1 branch operation – 1 condition register operation – 1 vector permute operation – 1 vector ALU operation – 32 64 bit general purpose registers, 32 64 bit ● floating point registers, 32 128 vector registers Pipeline Ref 4 Benchmarks SPEC2000 ● BLAST – Bioinformatics ● Amber / jac - Structure biology ● CFD lab code ●