UUnniivveerrssiittyy ooff WWiinnddssoorr SScchhoollaarrsshhiipp aatt UUWWiinnddssoorr Electronic Theses and Dissertations Theses, Dissertations, and Major Papers 2011 HHyybbrriidd MMOOSS aanndd SSiinnggllee--EElleeccttrroonn TTrraannssiissttoorr AArrcchhiitteeccttuurreess ttoowwaarrddss AArriitthhmmeettiicc AApppplliiccaattiioonnss Guoqing Deng University of Windsor Follow this and additional works at: https://scholar.uwindsor.ca/etd RReeccoommmmeennddeedd CCiittaattiioonn Deng, Guoqing, "Hybrid MOS and Single-Electron Transistor Architectures towards Arithmetic Applications" (2011). Electronic Theses and Dissertations. 5390. https://scholar.uwindsor.ca/etd/5390 This online database contains the full-text of PhD dissertations and Masters’ theses of University of Windsor students from 1954 forward. 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Hybrid MOS and Single-Electron Transistor Architectures towards Arithmetic Applications by Guoqing Deng A Dissertation Submitted to the Faculty of Graduate Studies through the Department of Electrical and Computer Engineering in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy at the University of Windsor Windsor, Ontario, Canada 2011 © 2011 Guoqing Deng Declaration of Co-Authorship / Previous Publication I. Co-Authorship Declaration I hereby declare that this thesis incorporates materials that are the result of research taken under the supervision of my supervisor Dr. C. Chen. Results related to this research are reported in Chapters 3 through 6, inclusive. I am aware of the University of Windsor Senate Policy on Authorship and I certify that I have properly acknowledged the contribution of other researchers to my thesis, and have obtained written permission from my co-author to include aforementioned materials in my thesis. I certify that, with the above qualification, this thesis, and the research to which it refers, is the product of my own work. II. Declaration of Previous Publication This thesis includes seven original papers that have been previously published / submitted for publication in peer reviewed conferences and journals, as follows: iii Thesis Publication Publication title / full citation Chapter status G. Deng and C. Chen, “Performance Analysis and Improvement for Hybrid CMOS-SET Circuit Architectures,” published in Proc. 1st Microsystems and Nanoelectronics Research Conf. (MNRC), Ottawa, Canada, 2008, pp. 109-112. Chapter 3 G. Deng and C. Chen, “Towards Robust Design of Hybrid CMOS-SETs using Feedback Architectures,” in Proc. 10th published IEEE-NANO, Seoul, Korea, 2010, pp. 1125-1129. G. Deng and C. Chen, “Full Adder Design using Hybrid CMOS-SET Parallel Architectures,” in Proc. 9th IEEE- published NANO, Genoa, Italy, 2009, pp. 206-209. Chapter 4 G. Deng and C. Chen, “Hybrid CMOS-SET Arithmetic Circuit Design using Coulomb Blockade Oscillation published Characteristic,” Journal of Computational and Theoretical Nanoscience (JCTN), vol. 8, no. 8, pp. 1520-1526, Aug. 2011. G. Deng and C. Chen, “Binary Multiplication using Hybrid Chapter 5 MOS and Multigate Single-Electron Transistors,” IEEE submitted Transactions on Nanotechnology, July, 2011 (9 pages). G. Deng and C. Chen, “A Hybrid CMOS-SET Multiplier using Frequency Modulation,” in Proc. 11th IEEE-NANO, published Portland, Oregon, 2011, pp. 1167-1170. Chapter 6 G. Deng and C. Chen, “Frequency Synthesis for Arithmetic Operations using SET/MOS Hybrid Architectures,” IEEE submitted Transactions on VLSI Systems, August, 2011 (7 pages). iv I certify that I have obtained a written permission from the copyright owner to include the above published materials in my thesis. I certify that the above materials describe work completed during my registration as graduate student at the University of Windsor. I declare that, to the best of my knowledge, my thesis does not infringe upon anyone’s copyright nor violate any proprietary rights and that any ideas, techniques, quotations, or any other material from the work of other people included in my thesis, published or otherwise, are fully acknowledged in accordance with the standard referencing practices. Furthermore, to the extent that I have included copyrighted material that surpasses the bounds of fair dealing within the meaning of the Canada Copyright Act, I certify that I have obtained a written permission from the copyright owners to include such materials in my thesis. I declare that this is a true copy of my thesis, including any final revisions, as approved by my thesis committee and the Graduate Studies office, and that this thesis has not been submitted for a higher degree to any other University or Institution. v Abstract Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and Single-Electron Transistor (SET) hybrid architectures, which combine the merits of both MOSFET and SET, promise to be a practical implementation for nanometer-scale circuit design. In this thesis, we design arithmetic circuits, including adders and multipliers, using SET/MOS hybrid architectures with the goal of reducing circuit area and power dissipation and improving circuit reliability. Thanks to the Coulomb blockade oscillation characteristic of SET, the design of SET/MOS hybrid adders becomes very simple, and requires only a few transistors by using the proposed schemes of multiple-valued logic (MVL), phase modulation, and frequency modulation. The phase and frequency modulation schemes are also further utilized for the design of multipliers with more discussions. Two types of SET/MOS hybrid multipliers are presented in this thesis. One is the binary tree multiplier which adopts conventional tree structures with multi-input counters (or compressors) implemented with the phase modulation scheme. Compared to conventional CMOS tree multipliers, the area and power dissipation of the proposed multiplier are reduced by half. The other is the frequency modulated multiplier following a novel design methodology where the information is processed in the frequency domain. vi This method involves the design of digital-to-frequency and frequency-to-digital conversions which are also implemented with SET/MOS hybrid architectures. In this context, we explore the implicit frequency properties of SET, including both frequency gain and frequency mixing. The major merits of this type of multiplier include: a) simplicity of circuit structure, and b) high immunity against background charges within SET islands. One of the biggest challenges associated with SET-based circuits is the background charge effect. Background charges are mainly induced by defects or impurities located within the oxide barriers, and cannot be entirely removed by today’s technology. Since these random charges deteriorate the circuit reliability, we investigate different circuit solutions, such as feedback structure and frequency modulation, in order to counteract this problem. The feedback represents an error detection and correction mechanism which offsets the background charge effect by applying an appropriate voltage through an additional gate of SET. The frequency modulation, on the other hand, exploits the fact that background charges only shift the phase of Coulomb blockade oscillation without changing its amplitude and periodicity. Therefore, SET/MOS hybrid adders and multipliers using the frequency modulation scheme exhibit the high immunity against these undesired charges. vii To my wife, Jieqiong Gu. viii Acknowledgments This research would not have completed without the support and encouragement from my supervisor, peers, and family. I would like to express my sincerest gratitude to my supervisor, Dr. C. Chen, who has been providing me continuous support throughout my graduate studies. I am very grateful to him for his academic guidance which inspires me and drives me to complete this research work in time. I would like to thank my committee members, Dr. S. Chowdhury and Dr. M. Mirhassani from the Electrical and Computer Engineering, and Dr. S. Holger Eichhorn from Chemistry and Biochemistry, for their valuable advice during my seminars and constructive comments on this thesis. A special thank to Dr. R. Rashidzadeh who has instructed me to conduct simulations at the Research Centre for Integrated Microsystems (RCIM), and Dr. H. Wu who has influenced me with his graduate teaching. Finally, to my wife, my parents, and my parents-in-law, I am grateful for their support, encouragement, and understanding. My wife, Jieqiong Gu, always believed in me and stimulated me toward the success. She will be the true love of my entire life forever. ix Contents Declaration of Co-Authorship / Previous Publication ..................... iii Abstract ............................................................................................... vi Dedication. ......................................................................................... viii Acknowledgments ............................................................................... ix List of Figures ................................................................................... xiv List of Tables ................................................................................... xviii List of Abbreviations ........................................................................ xix List of Symbols .................................................................................. xxi 1. Introduction ..................................................................................... 1 1.1 Motivations ............................................................................................................. 1 1.2 Single-Electron-Tunneling Technology .................................................................. 2 1.3 Research Objectives ................................................................................................ 2 1.4 Thesis Organization ................................................................................................ 3 2. SET Background .............................................................................. 6 2.1 Single-Electron Scaling .......................................................................................... 6 2.2 Orthodox Theory ..................................................................................................... 8 2.3 SET Structure .......................................................................................................... 9 2.4 Coulomb Blockade Oscillation ............................................................................. 11 2.5 Simulation Techniques.......................................................................................... 16 x