High Power LDMOS L-Band Radar Amplifiers by Stuart Roderick Arthur McIver Thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Engineering at Stellenbosch University Supervisors: Dr C van Niekerk, Prof P.W. Van Der Walt Department of Electrical and Electronic Engineering March 2010 Declaration By submitting this thesis electronically, I declare that the entirety of the work contained therein is my own, original work, that I am the owner of the copyright thereof (unless to the extent explicitly otherwise stated) and that I have not previously in its entirety or in part submitted it for obtaining any qualification. March 2010 Copyright © 2010 Stellenbosch University All rights reserved i Abstract The thesis details the design, construction and experimental evaluation of 30W, 35W and 250W L-Band LDMOS Radar amplifiers. Each amplifier module contains an integrated high speed power supply in order to optimize RF pulse repeatability and to improve radar MTI factor (Moving Target Indication.) As part of the work, a pulsed RF measurement system for measuring the dynamic I-V curves of a power FET was developed. Work was also done on low impedance S-parameter measurement test fixtures for the characterisation of power FETs. These measurement systems generated design information which was used in the development of the L- Band power amplifiers. ii Opsomming Hierdie tesis beskryf die ontwerp, bou en experimentele evaluering van „n 30W, 35W en 250W L-band LDMOS radarversterker. Elke versterker bevat ook „n geintegreerde hoë-spoed kragbron om optimum RF pulsherhaalbaarheid te verseker en die radar se „MTI (Moving Target Indication)‟ te verbeter. „n RF- pulsmetingstelsel is ook ontwikkel om die dinamiese I-V kurwes van „n hoë-krag FET te meet. Verder is daar ook gewerk aan „n toetsopstelling vir lae-impedansie S-parameters om hoë-krag FETs te karakteriseer. Hierdie toetsopstelling is gebruik om ontwerpsdata te genereer wat gebruik is in die ontwerp van die L-band kragversterkers. iii Table of Contents Declaration ............................................................................................................................................................... i Abstract.................................................................................................................................................................... ii Opsomming ............................................................................................................................................................ iii Table of Contents.................................................................................................................................................... iv List of Figures ........................................................................................................................................................ vii List of Tables .......................................................................................................................................................... xi Chapter 1 – Introduction .......................................................................................................................................... 1 1.1 History of Amplifiers ................................................................................................................................... 1 1.2 Background to Power Amplifier Design ...................................................................................................... 1 1.3 Power Amplifier Design in RADAR Applications ...................................................................................... 3 1.4 Problem Statement ....................................................................................................................................... 3 1.5 Investigation Aims ....................................................................................................................................... 4 1.6 Thesis Approach .......................................................................................................................................... 5 Chapter 2 - Pulsed I-V Measurement System Design ............................................................................................. 7 2.1 Introduction .................................................................................................................................................. 7 2.2 System Overview ......................................................................................................................................... 8 2.3 Gate Pulser ................................................................................................................................................... 9 2.3.1 Sinusoidal Signal Generation ............................................................................................................. 10 2.3.2 External Signal Relay ......................................................................................................................... 13 2.3.3 Amplitude Variation........................................................................................................................... 13 2.2.4 Level Detection .................................................................................................................................. 14 2.3.5 DC and Level Addition ...................................................................................................................... 15 2.3.6 Pulse Modulation ............................................................................................................................... 16 2.4 Test Fixture for Power FETS ................................................................................................................ 16 2.5 Control System .......................................................................................................................................... 18 2.7 Calibration ................................................................................................................................................. 19 2.8 Results ........................................................................................................................................................ 20 2.9 Recommended System Improvements ....................................................................................................... 23 2.10 Conclusions .............................................................................................................................................. 23 Chapter 3 - Advanced Low Impedance TRL Fixture ............................................................................................ 24 3.1 Introduction ................................................................................................................................................ 24 3.2 Low Impedance TRL design ...................................................................................................................... 24 3.2.1 Klopfenstein Taper Design................................................................................................................. 24 3.2.2 Mechanical Fixture Design ................................................................................................................ 26 3.3 Testing and Validation ............................................................................................................................... 32 iv 3.4 Conclusion ................................................................................................................................................. 37 Chapter 4 - LDMOS Equivalent Circuit Parameter Extraction ............................................................................. 38 4.1 Introduction ................................................................................................................................................ 38 4.2 LDMOS Package Parameter Extraction..................................................................................................... 38 4.3 Extrinsic Parameter Extraction .................................................................................................................. 42 4.4 Intrinsic Parameter Extraction ................................................................................................................... 46 4.5 Conclusion ................................................................................................................................................. 53 Chapter 5 – Power Supply Design ......................................................................................................................... 54 5.1 Introduction ................................................................................................................................................ 54 5.2 Operating Principals................................................................................................................................... 54 5.3 Practical Implementation ........................................................................................................................... 55 5.4 Test and Evaluation ................................................................................................................................... 56 5.5 Conclusion ................................................................................................................................................. 59 Chapter 6 – BLF2045 Amplifier Design ............................................................................................................... 60 6.1 Introduction ................................................................................................................................................ 60 6.2 Amplifier Design ....................................................................................................................................... 61 6.2.1 Optimum Load Line placement .......................................................................................................... 61 6.2.2 Output Network Design to Achieve Power Match ............................................................................. 62 6.2.2.1 Output Bias Network Design .......................................................................................................... 62 6.2.3 Input DC Bias Network Design ......................................................................................................... 66 6.2.4 Input Matching Network Design ........................................................................................................ 67 6.3 Results ........................................................................................................................................................ 70 6.3.1 Measurement setup............................................................................................................................. 70 6.4 Conclusion ................................................................................................................................................. 76 Chapter 7 – BLL1214-35 RADAR Amplifier Design ........................................................................................... 77 7.1 Introduction ................................................................................................................................................ 77 7.2 Design ........................................................................................................................................................ 78 7.2.1 S-Parameter Measurement ................................................................................................................. 78 7.2.2 Output DC Bias Network Design ....................................................................................................... 78 7.2.3 Output Impedance Matching Network Design ................................................................................... 79 7.2.4 Input DC Bias Network Design ......................................................................................................... 80 7.2.5 Input Impedance Matching Network Design ..................................................................................... 80 7.3 Measurement Setup .................................................................................................................................... 83 7.4 Results ........................................................................................................................................................ 84 7.4.1 Recommendations .............................................................................................................................. 88 7.5 Conclusion ................................................................................................................................................. 89 Chapter 8 – BLL1214-250 RADAR Amplifier Design ......................................................................................... 90 v 8.1 Introduction ................................................................................................................................................ 90 8.2 Design ........................................................................................................................................................ 91 8.2.1 S-Parameter Measurement ................................................................................................................. 91 8.2.2 Output DC Bias Network Design ....................................................................................................... 91 8.2.3 Output Impedance Matching Network Design ................................................................................... 91 8.2.4 Input DC Bias Network Design ......................................................................................................... 92 8.2.5 Input Impedance Matching Network Design ..................................................................................... 93 8.3 Measurement Setup .................................................................................................................................... 96 8.4 Results ........................................................................................................................................................ 98 8.4.1 Recommendations ............................................................................................................................ 103 8.5 Conclusion ............................................................................................................................................... 104 Chapter 9 – General Conclusion .......................................................................................................................... 109 9.1 Conclusion ............................................................................................................................................... 109 9.2 Recommendations .................................................................................................................................... 110 Bibliography ........................................................................................................................................................ 111 vi List of Figures Figure 1 - Layout of a typical cascaded power amplifier system which includes driver amplifiers, main power amplifiers as well as splitters, combiners, circulators and high power 50 Ohm terminations used to dissipate any reflected power. ...................................................................................................................................................... 4 Figure 2 - Diagram showing the approach to the thesis. The diagram shows the steps required to design the three amplifiers as well as the flow of information generated by the stages. .................................................................. 5 Figure 3 - A figure showing an example of a pulsed sinusoidal signal applied to the gate of the DUT in order to generate the required I-V curves. The signal shows gate voltage against time...................................................... 8 Figure 4 - A figure showing pulsed measurement system overview including the control equipment needed to automate the measurement. .................................................................................................................................... 9 Figure 5 – Figure full schematic of gate pulser system ........................................................................................ 11 Figure 6 - Figure showing the schematic of active diode full-wave rectifier ....................................................... 15 Figure 7 - Figure showing final Pulsed I-V measurement setup ........................................................................... 16 Figure 8 - Figure of gate driver block and DUT fixture block.............................................................................. 17 Figure 9 - Photo of fixture assembly shown in two separate sections. The section on the left shows the pulsed I- V signal generation circuit. The section on the right shows the gate driver amplifiers attached to the power FET test fixture ............................................................................................................................................................. 18 Figure 10 - Figure showing schematic of the control system. .............................................................................. 19 Figure 11 - Figure showing pulsed RF I-V curve of Silicon Carbide transistor P259_4_T03F3 ......................... 20 Figure 12 - Figure showing pulsed DC I-V curve of Silicon Carbide transistor P259_4_T03F3 ......................... 21 Figure 13 - Diagram comparing the measured Ids of RF vs. DC pulsed measurements ...................................... 21 Figure 14 - Graph showing pulsed RF I-V curves for BLF2045 LDMOS device ................................................ 22 Figure 15 - Graph showing DC I-V curves for various V of the BLF2045 LDMOS device. ............................ 22 GS Figure 16 - Figure Showing Klopfenstein Taper Profile of BLF2045 and BLL1214-35 measurement fixtures including mounting holes for screws. ................................................................................................................... 25 Figure 17 - Figure showing the coaxial to microstrip conversion including the dimensioning of the coaxial to microstrip transition implemented in order to maintain a 50 Ω impedance. ......................................................... 27 Figure 18 - Figure showing approximation of the cross section of a waveguide channel at coaxial-microstrip transition ............................................................................................................................................................... 28 Figure 19 - Figure showing the design plan of the calibration standards as well as their launch lines and calibration planes. ................................................................................................................................................. 28 Figure 20 - Figure showing the cross section of the DUT fixture block ............................................................... 30 Figure 21 - Figure showing the possible step discontinuity in the ground surface of two fixture blocks ............. 31 Figure 22 - Figure showing the connection between two blocks .......................................................................... 31 Figure 23 - Figure showing the final Low-Impedance Test Fixture including calibration standards ................... 32 Figure 24 – Figure showing the representation of the low impedance TRL validation system. Two transmission lines are represented. The un-calibrated VNA, cable and fixture errors are represented by the matrixes X and Y. The transmission lines are represented by matrixes Ti and Tj............................................................................... 33 Figure 25 - Graph showing effective ε as well as areas of validity and variation due to length differences for the r various transmission line combinations ................................................................................................................ 36 vii Figure 26 - Figure showing the open and "short-all" packages of the BLF2045 .................................................. 39 Figure 27 - Figure showing the open standard BLL1214-35 model ..................................................................... 39 Figure 28 - Figure showing the 'short-all' standard BLL1214-35 model .............................................................. 40 Figure 29 - Figure showing the Smith chart of the measured vs. the simulated S11 data of the open and short standards ............................................................................................................................................................... 41 Figure 30 - Figure showing the Smith chart of the measured vs. the simulated S22 data of the open and 'short-all' standards ............................................................................................................................................................... 41 Figure 31 - Figure showing the model of both the package parameters and the extrinsic bond wire parameters of a BLF2045 transistor. This model is used for calculations but not to represent the device. ................................. 43 Figure 32 - Figure showing the model of both the package parameters and the extrinsic bond wire parameters of a BLF2045 transistor. This model is used for calculations but not to represent the device. ................................. 44 Figure 33 - Figure showing the S11 of the cold data measurement vs. the model measurements for the BLF2045 device .................................................................................................................................................................... 44 Figure 34 - Figure showing the S22 of the cold data measurement vs. the model measurements for the BLF2045 device .................................................................................................................................................................... 45 Figure 35 - Figure showing the intrinsic small signal device model within the extrinsic and package elements. The bond wire capacitances are included in the small signal device model. ........................................................ 47 Figure 36 - Figure showing the intrinsic small signal parameter model ............................................................... 47 Figure 37 - Figure showing the measured S21 of the BLF2045 vs. the optimised model response ..................... 49 Figure 38 - showing the measured S12 of the BLF2045 vs. the optimised model response................................. 50 Figure 39 - showing the measured magnitude of the S21 of the BLF2045 vs. the optimised model response ..... 51 Figure 40 - showing the measured input reflection S11 of the BLF2045 vs. the optimised model response ....... 51 Figure 41 - showing the measured output reflection S22 of the BLF2045 vs. the optimised model response ..... 52 Figure 42 - Block Diagram of pulsed power supply ............................................................................................. 54 Figure 43 - Figure showing model schematic used in the simulation of the pulsed power supply including the distributed capacitor model used to predict the pulsed response of the power supply ......................................... 55 Figure 44 - Figure showing output voltage of power supply during initial tests at the maximum specifications of 10% duty cycle and 100us pulse length ................................................................................................................ 57 Figure 45 - Figure showing power supply AC ripple during initial tests at the maximum specifications of 10% duty cycle and 100us pulse length. ....................................................................................................................... 57 Figure 46 - Figure showing the power supply connected to the BLL1214-250 250W amplifier used in the final power supply evaluation. ...................................................................................................................................... 58 Figure 47 - Figure showing measured power supply ripple during final BLL1214-250 250W amplifier operation at output power of +-54dBm at a 10% duty cycle. ............................................................................................... 58 Figure 48 - Figure showing the normalised power output of the BLL1214-250 250W amplifier, indicating the power supply‟s ability to rapidly supply current to the amplifier. ........................................................................ 59 Figure 49 - Figure showing the pulsed I-V curve and load line placement .......................................................... 61 Figure 50 - Figure showing the model layout of the output DC bias network ...................................................... 62 Figure 51 - Figure showing the smith chart of the output DC bias network ......................................................... 63 viii Figure 52 - Figure showing the schematic of the load as seen from the current source within the BLF2045 including the output matching network which takes the DC bias network into account ...................................... 63 Figure 53 - Figure showing the simulation of the final load as seen from the current source after optimisation . 65 Figure 54 - Figure showing the final output matching network of the BLF2045 amplifier including the DC bias network, the impedance transformation network and the DC de-coupling capacitor ........................................... 65 Figure 55 - Figure showing the design of the output DC bias network ................................................................ 66 Figure 56 - Figure showing the final simulated S11 and S22 of the amplifier within the operating L-Band ....... 67 Figure 57 - Figure showing the simulated S11 and S22 of the final amplifier over from 0.5-2Ghz ..................... 68 Figure 58 - Figure showing the smith chart of S11 and S22 of the final BLF2045 amplifier design ................... 68 Figure 59 - Figure showing the simulated S21 of the final BLF2045 amplifier design from 0.5-2GHz .............. 69 Figure 60 - Figure showing graphs of μ1 and μ2 stability criteria ........................................................................ 70 Figure 61 - Figure showing the setup to test the stability of a DUT ..................................................................... 71 Figure 62 - Figure showing the measured small signal s-parameter S11 measurement of the BLF2045 30W amplifier ............................................................................................................................................................... 72 Figure 63 - Figure showing the measured small signal S21 gain measurement of the BLF2045 30W amplifier . 73 Figure 64 - Figure showing the equipment setup used to measure the high power response of the BLF2045 ..... 74 Figure 65 - Figure showing the measured BLF2045 amplifiers Output Power vs. Frequencies for various Input Powers .................................................................................................................................................................. 74 Figure 66 - Figure showing the measured results from the BLF2045 amplifier showing the Output power vs. the Input power for various frequencies ..................................................................................................................... 75 Figure 67 - Figure showing the measured results from the BLF2045 amplifier showing the Drain Current (Ids) vs Input Power for various frequencies ................................................................................................................ 75 Figure 68 - Graph Showing S-Parameter Measurement of BLL1214-35 gained from Low Impedance TRL Test Fixture .................................................................................................................................................................. 78 Figure 69 - Figure Showing Simulated Load Impedance vs. Recommended Load Impedance ........................... 80 Figure 70 - Figure showing the final layout of the BLL1214-35 amplifier including both the input and output matching networks ................................................................................................................................................ 81 Figure 71 - Figure Showing Simulated Input and Output Matching of BLL1214-35 35W Amplifier ................. 82 Figure 72 – Figure showing Simulated Gain (S21) of BLL1214-35 35W Amplifier ........................................... 82 Figure 73 – Figure showing Simulated Stability Circle Analysis of BLL1214-35 35W Amplifier ..................... 83 Figure 74 - Figure showing the Input Match-S11 of the BLL1214-35 35W amplifier for various DC bias points .............................................................................................................................................................................. 84 Figure 75 - Figure showing the Gain-S21 of the BLL1214-35 35W amplifier for various DC bias points ......... 85 Figure 76 - Figure showing the output power of the BLL1214-35 35W amplifier with respect to the input power .............................................................................................................................................................................. 85 Figure 77 - Figure showing the Output power of the BLL1214-35 35W amplifier with respect to the frequency .............................................................................................................................................................................. 86 Figure 78 - Figure showing the gain of the BLL1214-35 35W amplifier with respect to the input power........... 87 Figure 79 - Figure showing the gain of the BLL1214-35 35W amplifier with respect to frequency.................... 88 ix