Flexible and self-calibrating current-steering digital-to-analog converters : analysis, classification and design Citation for published version (APA): Radulov, G. I. (2010). Flexible and self-calibrating current-steering digital-to-analog converters : analysis, classification and design. [Phd Thesis 1 (Research TU/e / Graduation TU/e), Electrical Engineering]. Technische Universiteit Eindhoven. https://doi.org/10.6100/IR656902 DOI: 10.6100/IR656902 Document status and date: Published: 01/01/2010 Document Version: Publisher’s PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. 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If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the “Taverne” license above, please follow below link for the End User Agreement: www.tue.nl/taverne Take down policy If you believe that this document breaches copyright please contact us at: [email protected] providing details and we will investigate your claim. Download date: 21. Jan. 2023 Flexible and self-calibrating current- steering Digital-to-Analog Converters: analysis, classification and design PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Eindhoven, op gezag van de rector magnificus, prof.dr.ir. C.J. van Duijn, voor een commissie aangewezen door het College voor Promoties in het openbaar te verdedigen op dinsdag 14 januari 2010 om 16.00 uur door Georgi Ivanov Radulov geboren te Plovdiv, Bulgarije Dit proefschrift is goedgekeurd door de promotor: prof.dr.ir. A.H.M. van Roermund Copromotoren: dr.ir. J.A. Hegt en dr. P.J. Quinn MSc A catalogue record is available from the Eindhoven University of Technology Library ISBN: 978-90-386-2125-8 - 3 - To Ivan and Elissaveta - 4 - This research work has been financially supported by the Dutch Technical Foundation STW, project ECS.6098. This research work has been technically supported by Xilinx Ireland, Mixed-Signal Design Group. This research work has been realized in the Mixed-Signal Microelectronics group at the Electrical Engineering faculty of the Eindhoven University of Technology. - 5 - ABSTRACT This research work proposes new concepts of flexibility and self-correction for current- steering digital-to-analog converters (DACs) which allow the attainment of broad functional and performance specifications, high linearity, and reduced dependence on the fabrication processes. This work analytically investigates the DAC linearity with respect to the accuracy of the DAC unit elements. The main novelty of the proposed approach is in the application of the Brownian Bridge (BB) process to precisely describe the DAC Integrated-Non-Linearity (INL). The achieved results fill a gap in the general understanding of the most quoted DAC specification - the INL. Further, this work introduces a classification of the highly diverse current-steering DAC correction methods. The classification automatically points to methods that do not exist yet in the open literature (gaps). Based on the clues of the common properties and identified common techniques in the introduced classification, this work then proposes exemplary solutions to fill in the identified gaps. Further, this work systematically analyses self-calibration correction methods for the DAC mismatch errors. Their components are analyzed as three building blocks: self- measurement, error processing algorithm and self-correction block. This work systemizes their alternative implementations and the associated trade-offs. The findings are compared to the available solutions in the literature. The efficient calibration of the DAC binary currents is identified as an important missing method. This work proposes a new methodology for correcting the mismatch errors of both the nominally identical unary and the scaled binary DAC currents. Further, this work proposes a new concept for DAC flexibility. This concept is realized in a new flexible DAC architecture. The architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, flexible functionality and flexible performance. The parallel sub-DAC units form a mixed-signal platform that is capable of many DAC correction methods, including calibration, error mapping, data reshuffling, and harmonic distortion cancellation. This work presents the implementation and measurement results of three DAC test- chip implementations in 250nm, 180nm, and 40nm standard CMOS IC technologies. The test-chips are used as a tool to practically investigate, validate, and demonstrate two main concepts of this thesis: self-calibration and flexibility. Particularly, the 180nm test-chip is the first reported DAC implementation that calibrates the errors of all its current sources and features flexibility, as suggested in this work. The calibration of all current sources makes the DAC accuracy independent of the tolerances of the manufacturing process. The overall DAC accuracy depends on a single design parameter – the correction step. The third test-chip is the first reported DAC implementation in 40nm CMOS process. A 12 bit DAC core in this test-chip occupies only 0.05mm2 of silicon area, which is the smallest reported area for a 12 bit current-steering DAC core. - 6 - LIST OF ABBREVIATIONS AC alternating current MOSFET metal-oxide-semiconductor field-effect transistor ADC analog-to-digital converter MSB most significant bit(s) ASIC application-specific integrated circuit NRZ non-return-to-zero BB Brownian Bridge OFDM orthogonal frequency division BIST built-in-self-test multiplexing CALDAC calibrating digital-to-analog PA power amplifier converter PCB printed circuit board CMOS complementary metal-oxide semiconductor PDF probability density function CS current steering PWM pulse-width modulated D/A digital-to-analog RAM random access memory DAC digital-to-analog converter RF radio frequency DC direct current RTL register transfer level DEM dynamic element matching RZ return-to-zero DNL differential non-linearity S/D source/drain DQS differential-quad-switching S/N signal-to-noise DR dynamic range SAR successive approximation register DSP digital signal processor (processing) SC switched-capacitor ENOB effective number of bits SI switched-current ETF error transfer function SFDR spurious-free dynamic range ETFP error-transfer-function-prevention SNR signal-to-noise ratio ETFC error-transfer-function-correction SNDR signal-to-noise-and-distortion-ratio FFT fast Fourier transform STFC signal-transfer-function- compensation FS full scale SPICE simulation program with integrated FPGA field-programmable gate array circuit emphasis HD harmonic distortion SoC system-on-chip HF high frequency STF signal transfer function I/O input/output T/H track and hold IC integrated circuit THD total harmonic distortion INL integrated non-linearity UHF ultra-high frequency IM inter modulation VCO voltage-controlled oscillator IMD inter-modulation distortion VHDL very high speed IC hardware LSB least significant bit(s) description language LUT look-up table VLSI very-large scale integration LVDS low voltage differential signaling WL area width times length area (of a MOS metal-oxide-semiconductor transistor) - 7 - TABLE OF CONTENTS LIST OF ABBREVIATIONS ....................................................................................................... 6 PART I: INTRODUCTION AND BASICS ............................................................................... 13 INTRODUCTION ....................................................................................................................... 14 1.1. MODERN MICRO-ELECTRONICS AND FLEXIBILITY ............................................................... 15 1.2. AIMS OF THE THESIS .......................................................................................................... 16 1.3. SCOPE OF THE THESIS ....................................................................................................... 16 1.4. SCIENTIFIC APPROACH....................................................................................................... 17 1.5. OUTLINE OF THE THESIS .................................................................................................... 18 1.6. ORIGINAL CONTRIBUTIONS ................................................................................................ 20 BASICS OF DIGITAL-TO-ANALOG CONVERSION ........................................................... 22 2.1. INTRODUCTION ................................................................................................................... 23 2.2. FUNCTIONALITY AND SPECIFICATIONS ............................................................................... 23 2.2.1. STATIC CHARACTERIZATION...............................................................................................23 2.2.2. DYNAMIC CHARACTERIZATION ...........................................................................................26 2.3. DAC RESOURCES .............................................................................................................. 27 2.4. SEGMENTATION OF DAC ANALOG RESOURCES ................................................................ 29 2.4.1. BINARY ALGORITHMIC SEGMENTATION .............................................................................30 2.4.2. SUB-BINARY RADIX ALGORITHMIC SEGMENTATION ..........................................................31 2.4.3. UNARY ALGORITHMIC SEGMENTATION ..............................................................................32 2.4.4. BINARY LSB AND UNARY MSB ALGORITHMIC SEGMENTATION .......................................32 2.5. DAC IMPLEMENTATIONS .................................................................................................... 33 2.6. CURRENT-STEERING DAC ARCHITECTURE ....................................................................... 34 2.7. MODERN CURRENT-STEERING DAC CHALLENGES............................................................ 36 2.8. SUMMARY .......................................................................................................................... 38 PART II: STATE-OF-THE-ART CORRECTION METHODS ............................................... 39 ERROR CORRECTION BY DESIGN ..................................................................................... 40 3.1. INTRODUCTION ................................................................................................................... 41 3.2. RETURN-TO-ZERO OUTPUT ................................................................................................ 41 3.3. DIFFERENTIAL-QUAD SWITCHING ...................................................................................... 43 3.4. CASCODE SWITCHES WITH OFFSET CURRENT.................................................................... 44 3.5. INPUT DATA RESHUFFLING METHODS (DEM) .................................................................... 45 3.6. DISCUSSION ....................................................................................................................... 47 3.7. CONCLUSIONS ................................................................................................................... 48 SMART SELF-CORRECTING D/A CONVERTERS ............................................................. 49 4.1. INTRODUCTION ................................................................................................................... 50 4.2. SELF-CALIBRATION OF DAC CURRENT CELLS .................................................................. 50 4.2.1. AMPLITUDE ERRORS SELF-CALIBRATION ..........................................................................51 4.2.2. TIMING ERRORS SELF-CALIBRATION ..................................................................................52 4.2.3. DISCUSSION ........................................................................................................................53 4.3. MAPPING ............................................................................................................................ 53 4.3.1. LOW LEVEL MAPS FOR DAC UNARY CURRENT CELLS ......................................................54 Table of contents - 8 - 4.3.2. LOW-LEVEL MAPS FOR SUB-BINARY RADIX DACS ............................................................ 57 4.4. DIGITAL PRE-DISTORTION .................................................................................................. 59 4.5. DISCUSSION ....................................................................................................................... 60 4.6. CONCLUSIONS ................................................................................................................... 61 PART III: NEW MODELING, ANALYSIS, AND CLASSIFICATION .................................. 63 ERROR MODELING FOR DAC CORRECTION, A BROAD VIEW ................................... 64 5.1. INTRODUCTION ................................................................................................................... 65 5.2. A MODEL OF THE STEP RESPONSE OF A CURRENT CELL ................................................... 66 5.3. TRANSISTOR MISMATCH CAUSED ERRORS ........................................................................ 67 5.4. DIGITAL-SWITCHING ERRORS ............................................................................................ 71 5.5. DISCUSSION ....................................................................................................................... 73 5.6. CONCLUSIONS ................................................................................................................... 74 BROWNIAN BRIDGE BASED ANALYSIS AND MODELING OF DAC LINEARITY, AN IN-DEPTH VIEW ........................................................................................................................ 75 6.1. INTRODUCTION ................................................................................................................... 76 6.2. NEW STATISTICAL ANALYSIS OF THE DAC STATIC NON-LINEARITY BASED ON BROWNIAN BRIDGE ........................................................................................................................................ 77 6.2.1. UNARY DAC ....................................................................................................................... 78 6.2.2. BINARY DAC ...................................................................................................................... 82 6.3. DISCUSSION ....................................................................................................................... 84 6.4. CONCLUSIONS ................................................................................................................... 86 CLASSIFICATION OF ERROR CORRECTION METHODS, A BROAD VIEW ............... 87 7.1. INTRODUCTION ................................................................................................................... 88 7.2. SELECTED SET OF DAC CORRECTION METHODS AND DEFINITIONS .................................. 88 7.3. ERROR MEASUREMENT CATEGORY ................................................................................... 91 7.4. REDUNDANCY CATEGORY ................................................................................................. 93 7.5. SYSTEM LEVEL CATEGORY ................................................................................................ 94 7.6. DISCUSSION ....................................................................................................................... 95 7.7. CONCLUSION ..................................................................................................................... 96 ANALYSIS OF SELF-CALIBRATION OF CURRENTS, AN IN-DEPTH VIEW ................ 97 8.1. INTRODUCTION ................................................................................................................... 98 8.2. DAC CURRENTS SELF-CALIBRATION CLASSIFICATION ...................................................... 98 8.3. SELF-MEASUREMENT ...................................................................................................... 100 8.3.1. MEASUREMENT PROBES ..................................................................................................100 8.3.1.1. Measurements at the upper voltage headroom ..................................................101 8.3.1.2. Measurements at the lower voltage headroom ..................................................102 8.3.1.3. Measurements at the middle voltage headroom ................................................102 8.3.1.4. Deterioration of the intrinsic DAC performance, discussion and comparison 103 8.3.1.4.1. Current source impedance ................................................................................104 8.3.1.4.2. Charge feed-through ..........................................................................................104 8.3.1.4.3. Alteration of the measured current ..................................................................105 8.3.1.4.4. Occupied silicon area .........................................................................................105 8.3.1.4.5. Voltage headroom range ...................................................................................105 8.3.2. REFERENCE ......................................................................................................................105 8.3.3. MEASUREMENT DEVICE....................................................................................................106 Table of contents - 9 - 8.3.3.1. Fully analog measurements .................................................................................. 106 8.3.3.2. ADC-based measurements ................................................................................... 107 8.3.3.2.1. Multi bit voltage ADC-based measurements ................................................ 107 8.3.3.2.2. Single bit voltage ADC-based measurements ............................................. 108 8.3.3.2.3. Single bit current ADC-based measurements .............................................. 109 8.3.3.2.3.1. Analog compensation of measurement errors ........................................ 109 8.3.3.2.3.2. Digital compensation of measurement errors ......................................... 111 8.3.3.2.3.3. Measurement-error insensitive approach ................................................ 112 8.3.3.3. Discussion ................................................................................................................. 113 8.4. ALGORITHM ...................................................................................................................... 113 8.4.1. UNARY-CURRENTS CALIBRATION.................................................................................... 114 8.4.2. NEW BINARY-CURRENTS CALIBRATION IN A UNARY WAY .............................................. 116 8.4.3. NEW TRUE BINARY-CURRENTS CALIBRATION................................................................. 117 8.5. SELF-CORRECTION .......................................................................................................... 121 8.5.1. SELF-CORRECTION METHOD ........................................................................................... 122 8.5.1.1. High level correction ............................................................................................... 122 8.5.1.2. Low level correction, inject or regulate ................................................................ 123 8.5.1.3. Low level correction, continuous or discrete ...................................................... 123 8.5.2. CORRECTION CIRCUITS ................................................................................................... 124 8.5.2.1. Gate-source voltage regulating circuits ............................................................... 124 8.5.2.2. Correction current injecting circuits ...................................................................... 125 8.5.3. CORRECTION MEMORY.................................................................................................... 126 8.6. CONCLUSIONS ................................................................................................................. 127 PART IV: NEW CONCEPTS AND METHODS .................................................................... 129 NEW REDUNDANT SEGMENTATION CONCEPT ............................................................ 130 9.1. INTRODUCTION ................................................................................................................. 131 9.2. ABSTRACTION LEVELS OF SEGMENTATION ...................................................................... 133 9.3. NEW REDUNDANT SEGMENTATION ................................................................................... 134 9.4. DISCUSSION ..................................................................................................................... 137 9.5. CONCLUSION ................................................................................................................... 138 NEW METHODS FOR SELF-CALIBRATION OF CURRENTS ........................................ 140 10.1. INTRODUCTION ............................................................................................................... 141 10.2. SELF-CALIBRATION OF UNARY CURRENTS ..................................................................... 141 10.2.1. NEW CALIBRATION METHOD .......................................................................................... 141 10.2.2. CONCLUSIONS ............................................................................................................... 146 10.3. A CALIBRATION METHOD FOR GENERIC CURRENT-STEERING D/A CONVERTERS WITH ........................................................................................................... 146 OPTIMAL AREA SOLUTION 10.3.1. NEW SELF-CALIBRATING CURRENT CELL FOR A GENERIC DAC ARCHITECTURE ....... 147 10.3.2. AREA DRIVEN OPTIMUM OF THE LEVEL OF CALIBRATION ............................................. 148 10.3.3. DISCUSSION ................................................................................................................... 150 10.3.4. CONCLUSIONS ............................................................................................................... 151 10.4. A CALIBRATION METHOD FOR BINARY SIGNAL CURRENT SOURCES .............................. 151 10.4.1. CALIBRATION OF SCALED CURRENTS ........................................................................... 152 10.4.2. CONCLUSIONS ............................................................................................................... 153 10.5. DISCUSSION ................................................................................................................... 154 10.6. CONCLUSIONS ............................................................................................................... 154 NEW REDUNDANT DECODER CONCEPT ........................................................................ 155 Table of contents