ErrorCancelingLowVoltageSAR-ADC by JianpingWen AThesis submittedto OregonStateUniversity inpartialfulfillmentof therequirementsfor the degreeof MasterofScience CompletedJuly26,2000 CommencementJune 2001 ACKNOWLEDGMENTS I would like to express my sincere and deep appreciation to my academic advi- sors,Dr. GaborC.TemesandDr. Un-KuMoon,fortheresearchprojectandexcellent academic environment they provided for me. I have been honored and privilegedto have worked under their supervision. Without their warm encouragement and aca- demic guidance as well as their generous support, it would be impossible for me to completetheworkpresentedinthisthesis. Special thanks are extended to Dr. Byung-Moo Min for his competent expertise incircuitdesignthatgreatlyhelpedmeinthetransistorlevelimplementationsofthe designed A/D converter. The author also wants to thank Dr. Kyoung-Rok Cho for thevaluablediscussionondigitalcircuitdesign. I wouldlike toexpressmyappreciation toDr. JohnT.Stonickfor manyenlight- eningdiscussionsandcommentsonmyresearch duringourregularweeklyresearch groupmeetings. I also would like to thank Prof. Robert J. Schultz for taking time out of his busy scheduletoserveastheGraduateCouncilRepresentativeofmycommittee. Manythanks,also,toMr. Jose´ Silvaforhiskindhelpwithhiswonderfulskillsin variousCAD tools. Withouthishelp, I couldnotbe able to completemythesisnow butIwouldstillbeexploringthedetailsofthosenecessaryCADtoolsformydesign. I wish to thank my colleagues in our research group, Mr. Tetsuya Kajita, Mr. Mustafa Keskin, Dr. Peter Kiss and Mr. Dong-Yang Chang, for discussionson vari- oustechnicalissuesonthisresearch project. I wish to express my thanks to National Semiconductor Corporation for their financial support to this project and their facilities for fabricating the prototype chip ofthisthesis. Finally,Iwouldliketodedicatethisthesistomywife,LichunJia,andmydaugh- ter, Xueyin Wen. I would not be able to finish this thesis without the support of my lovingfamily. TABLE OFCONTENTS Page Chapter1: Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 ThesisStructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Chapter2: MismatchErrorCancellationAlgorithm 5 2.1 ConceptualOperationofa SuccessiveApproximationADC . . . . . 5 2.2 CircuitNon-idealities . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 ANovelCapacitorMismatchErrorCancellationTechniqueforSwitched CapacitorSAR –ADC . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 ImprovementofMismatchErrorCancellationAlgorithm . . . . . . 16 Chapter3: PredictiveCorrelatedTripleSampling(CTS) 22 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 TheoreticalAnalysisofTheSwitchedCapacitorSAR –ADC . . . . 24 3.2.1 InitialCharges IntroducedbySampling . . . . . . . . . . . 24 3.2.2 Charge DomainAnalysisofNormalConvertingCycles . . . 27 3.2.3 CalculationofHarmonicDistortionafterCDS Compensation 31 3.2.4 DiscussionandConclusion . . . . . . . . . . . . . . . . . . 32 3.3 ImprovementofPredictiveCDS inSC SAR –ADC . . . . . . . . . 33 3.4 Verification of Predictive CTS by SWITCAP Simulations of SAR – ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Chapter4: DesignofA1.8VSwitchedCapacitorSAR –ADC 40 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2 DesignSpecifications . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.3 AnalogComponentDesign . . . . . . . . . . . . . . . . . . . . . . 42 4.4 DigitalComponentDesign . . . . . . . . . . . . . . . . . . . . . . 50 TABLE OFCONTENTS (Continued) Page 4.4.1 ClockGenerator . . . . . . . . . . . . . . . . . . . . . . . . 52 4.4.2 FiniteStateMachine . . . . . . . . . . . . . . . . . . . . . 56 4.5 FullChipSimulation . . . . . . . . . . . . . . . . . . . . . . . . . 57 Chapter5: SummaryandFutureWork 61 5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.2 PlanofFutureWork . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Bibliography 63 LIST OFFIGURES Figure Page 2.1 GeneralsuccessiveapproximationADC . . . . . . . . . . . . . . . 6 2.2 Circuitof16-bitswitched-capacitorSAR -A/Dconverter . . . . . 9 2.3 Circuitsofswitchsetting1throughswitchsetting4 . . . . . . . . . 10 2.4 Circuitsofswitchsetting5throughswitchsetting8 . . . . . . . . . 11 2.5 Circuitsofswitchsetting9throughswitchsetting12 . . . . . . . . 12 2.6 Circuitsofswitchsetting13andswitchsetting14 . . . . . . . . . . 13 2.7 MismatcherrorcancellationforADD/ADDoperation . . . . . . . . 14 3.1 Demonstrationofinputsignalsampling . . . . . . . . . . . . . . . 25 3.2 Demonstrationofnormalconvertingcycles . . . . . . . . . . . . . 27 3.3 Harmonic distortion caused by op-amp non-ideality still exists after normalCDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4 predictiveCTS operation . . . . . . . . . . . . . . . . . . . . . . . 35 3.5 Outputspectrumof a SAR–ADC withpredictiveCDS, op-amp ,nomismatchandparasitic . . . . . . . . (cid:0). .(cid:0). 36 (cid:1)(cid:1)(cid:1)(cid:2)(cid:3)(cid:4)(cid:0)(cid:1) (cid:0) (cid:2)(cid:3)(cid:5)(cid:4) 3.6 Outputspectrum of a SAR–ADC with predictiveCTS, op-amp ,nomismatchandparasitic . . . . . . . . (cid:0). .(cid:0). 37 (cid:1)(cid:1)(cid:1)(cid:2)(cid:3)(cid:4)(cid:0)(cid:1) (cid:0) (cid:2)(cid:3)(cid:5)(cid:4) 3.7 Outputspectrumof a SAR–ADC withpredictiveCDS. op-amp ,mismatchandparasiticexist . . . . . . . (cid:0). .(cid:0). 37 (cid:1)(cid:1)(cid:1)(cid:2)(cid:3)(cid:4)(cid:0)(cid:1) (cid:0) (cid:2)(cid:3)(cid:5)(cid:4) 3.8 Outputspectrum of a SAR–ADC with predictiveCTS. op-amp ,mismatchandparasiticexist . . . . . . . (cid:0). .(cid:0). 38 (cid:1)(cid:1)(cid:1)(cid:2)(cid:3)(cid:4)(cid:0)(cid:1) (cid:0) (cid:2)(cid:3)(cid:5)(cid:4) 4.1 Modification of circuit from normal predictive CDS to double pre- dictiveCDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2 Implementationofthecomparator . . . . . . . . . . . . . . . . . . 43 4.3 TwostageclassA/ABoperationalamplifier . . . . . . . . . . . . . 44 4.4 Biascircuitoftheoperationalamplifier . . . . . . . . . . . . . . . 44 LIST OFFIGURES(Continued) Figure Page 4.5 Switchedcapacitorcommonmodefeedback circuit . . . . . . . . . 44 4.6 Typical frequency response of the two stage class A/AB operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.7 Pre-amplifierofcomparator . . . . . . . . . . . . . . . . . . . . . . 47 4.8 Biascircuitofthepre-amplifierofcomparator . . . . . . . . . . . . 47 4.9 Comparatorlatch . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.10 NMOSswitch-onresistancevarieswithswitchsize . . . . . . . . . 49 4.11 CMOS switch-on resistance with different switch sizes vary with settlingvoltage . . . . . . .(cid:6). . . . . . . . . . . . . . . . . . . . . 49 4.12 CMOSswitch-ontransconductances and . . . . . . . . . . 51 (cid:7)(cid:2)(cid:1)(cid:3) (cid:7)(cid:2)(cid:1)(cid:4) 4.13 CMOSswitch-ontransconductance . . . . 51 (cid:7)(cid:2)(cid:1) (cid:0) (cid:7)(cid:2)(cid:1)(cid:3) (cid:4)(cid:7)(cid:2)(cid:1)(cid:4) (cid:0) (cid:5)(cid:8)(cid:6) 4.14 ToplevelofdigitalblockrelativetoanalogblockoftheSCSAR–ADC 52 4.15 Timingdiagramoftheclockgenerator . . . . . . . . . . . . . . . . 53 4.16 Circuitimplementationofclockgenerator . . . . . . . . . . . . . . 55 4.17 StatetransitiondiagramofSAR –ADC . . . . . . . . . . . . . . . 56 4.18 Circuitimplementationofstatemachine . . . . . . . . . . . . . . . 58 4.19 Outputspectrum of the switched capacitor SAR – ADC by full chip simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.20 Layoutoftheswitched-capacitorsuccessiveapproximationADC . . 60 LIST OFTABLES Table Page 2.1 ADD/ADDSequence . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 ADD/SUBSequence . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 SUB/ADDSequence . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4 SUB/SUB Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 SwitchedCapacitor SARADCSpecifications . . . . . . . . . . . . 41 ERRORCANCELINGLOWVOLTAGESAR-ADC Chapter 1 Introduction 1.1 Motivation Signalprocessingisoneofthemajorincentivestothefastdevelopmentofelectronic circuits. With the tremendous advancement of modern VLSI technology, people are abletobuildmoreandmorecomplexdigitalcircuitsonasinglechiptorealizesignal processing that is conventionallyachieved by analog circuits, because digitalcircuit has advantages over its analog counterpart in several aspects such as much lower noise sensitivity, excellent signal regenerating capability. and it is easier to realize designand testautomationas well. However,theobject ofsignalprocessing- phys- ical signals of the real world are always in analog form. Therefore, to facilitate the extensive DSP functions in the digital domain, interfaces between analog and digi- talblocksare omnipresentinallmodernmixedsignalprocessingintegratedcircuits. Analogtodigitaldataconvertersare amongthemajorcomponentsintheinterfaces. There are three conceptually distinct operations that are performed sequentially by an A/D converter [17]: (1) It samples a continuous-valued, continuous-timeana- logsignal;(2)itquantizesthesampledsignaltoafinitenumberoflevels;(3)itassign a digital code to the related quantized level. With this sequence of operations, any physicalsignal,nomatterifitismechanical,thermal,optical,acoustical,ormagnet- ical, once it has been transformed into electrical signal by a proper sensor, it can be 2 converted into digital signal by an A/D converter and processed conveniently with powerfuldigitalsignalprocessingcomponents,outofwhichvarioususefulinforma- tioncanbeextracted. Therearemanyapproachestorealizingtheanalog-to-digitalconversion. Someof thesetechniques,suchasflashandpipeline[10]A/Dconverterstradeoffaccuracyfor speed. Ontheotherendofthescalethehighestaccuracyisrealizedbyoversampling A/D converters [13, 15], which have high tolerance to technological imperfections and component parameter variations but low conversion speed and high power con- sumption. The compromise between conversion speed and accuracy is achieved by Nyquistrate A/D converterssuch as algorithmic[9, 11] and successiveapproximate A/Dconverters,whichhavemoderatespeedandmoderateprecision. Switched capacitor circuits have become popular because of their good linear- ity and dynamic range. Naturally, switched capacitor techniques are also applied to Nyquist rate A/D converters. However, if the conversions are realized by simple charge transfer between ratio-matched capacitors, as it did in the work of McCha- rles, et al. [11] as an early algorithmic A/D converter, the conversion accuracy will be fundamentally limited by the ratio accuracy. To overcome this problem, several circuit configurations have been proposed which perform the cyclic conversion in a capacitor ratio independent manner [8, 9, 20, 23]. In those approaches the conver- sion speed was sacrificed for ratio-independent property substantially. For instance, 6 clock cycles were needed for each bit’s conversion in the design of Li, et al. [9] compared to 2 clocks in [11]. The approach proposed by Onodera, et al. [14] was able to decrease the number of clocks down to 3 for each bit. A further improve- ment for conversionspeed withoutlosing the ratio-independent feature was realized by Zheng, et al. [26], where a fullydifferential circuit structure was used and only2 clocks were needed for each bit’s conversion, which has the same conversion speed