ENC28J60 Data Sheet Stand-Alone Ethernet Controller with SPI™ Interface Advance Information  2004 Microchip Technology Inc. DS39662A Note the following details of the code protection feature on Microchip devices: (cid:127) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:127) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PROMATE, PowerSmart, rfPIC, and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR WAR- registered trademarks of Microchip Technology Incorporated RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, in the U.S.A. and other countries. WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, PICMASTER, SEEVAL, SmartSensor and The Embedded MERCHANTABILITY OR FITNESS FOR PURPOSE. Control Solutions Company are registered trademarks of Microchip disclaims all liability arising from this information and Microchip Technology Incorporated in the U.S.A. its use. Use of Microchip’s products as critical components in Analog-for-the-Digital Age, Application Maestro, dsPICDEM, life support systems is not authorized except with express dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, written approval by Microchip. No licenses are conveyed, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial implicitly or otherwise, under any Microchip intellectual property Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, rights. MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Advance Information DS39662A-page ii  2004 Microchip Technology Inc. ENC28J60 Stand-Alone Ethernet Controller with SPI™ Interface Ethernet Controller Features Operational (cid:127) IEEE 802.3 compatible Ethernet controller (cid:127) Two programmable LED outputs for LINK, TX, (cid:127) Integrated MAC and 10BASE-T PHY RX, collision and full/half-duplex status (cid:127) Receiver and collision squelch circuit (cid:127) Seven interrupt sources with two interrupt pins (cid:127) Supports one 10BASE-T port with automatic (cid:127) 25MHz clock polarity detection and correction (cid:127) Clock out pin with programmable prescaler (cid:127) Supports Full and Half-Duplex modes (cid:127) Operating voltage range of 3.14V to 3.45V (cid:127) Programmable automatic retransmit on collision (cid:127) TTL level inputs (cid:127) Programmable padding and CRC generation (cid:127) Temperature range: -40°C to +85°C Industrial, (cid:127) Programmable automatic rejection of erroneous 0°C to +70°C Commercial (SSOP only) packets (cid:127) 28-pin SPDIP, SSOP, SOIC, QFN packages (cid:127) SPI™ Interface with speeds up to 10Mb/s Package Types Buffer 28-Pin SPDIP, SSOP, SOIC (cid:127) 8-Kbyte transmit/receive packet dual port SRAM (cid:127) Configurable transmit/receive buffer size VCAP 1 28 VDD VSS 2 27 LEDA (cid:127) Hardware-managed circular receive FIFO CLKOUT 3 26 LEDB (cid:127) Byte-wide random and sequential access with INT 4 25 VDDOSC WOL 5 0 24 OSC2 auto-increment 6 SO 6 J 23 OSC1 (cid:127) Internal DMA for fast data movement SI 7 28 22 VSSOSC (cid:127) Hardware assisted IP checksum calculation SCK 8 NC 21 VSSPLL CS 9 E 20 VDDPLL RESET 10 19 VDDRX Medium Access Controller (MAC) VSSRX 11 18 VSSTX Features TPIN- 12 17 TPOUT+ TPIN+ 13 16 TPOUT- (cid:127) Supports Unicast, Multicast and Broadcast RBIAS 14 15 VDDTX packets (cid:127) Programmable receive packet filtering and 28-pin QFN wake-up host on logical AND or OR of the T U f-olUlonwicinags:t destination address INTCLKOVSSVCAPVDD LEDALEDB - Multicast address - Broadcast address - Magic Packet™ 28272625242322 - Group destination addresses as defined by WOL 1 21 VDDOSC SO 2 20 OSC2 64-bit hash table SI 3 19 OSC1 - Programmable pattern matching of up to SCK 4 ENC28J60 18 VSSOSC 64 bytes at user-defined offset CS 5 17 VSSPLL (cid:127) Loopback mode RESET 6 16 VDDPLL VSSRX 7 15 VDDRX 8 91011121314 Physical Layer (PHY) Features (cid:127) Wave shaping output filter (cid:127) Loopback mode TPIN- TPIN+ RBIASVDDTX TPOUT-TPOUT+VSSTX Advance Information  2004 Microchip Technology Inc. DS39662A-page 1 ENC28J60 Table of Contents 1.0 Overview......................................................................................................................................................................................3 2.0 External Connections...................................................................................................................................................................5 3.0 Memory Organization.................................................................................................................................................................11 4.0 Serial Peripheral Interface (SPI).................................................................................................................................................25 5.0 Ethernet Overview......................................................................................................................................................................31 6.0 Initialization.................................................................................................................................................................................33 7.0 Transmitting and Receiving Packets..........................................................................................................................................39 8.0 Receive Filters............................................................................................................................................................................47 9.0 Duplex Mode Configuration and Negotiation..............................................................................................................................53 10.0 Flow Control...............................................................................................................................................................................55 11.0 Reset..........................................................................................................................................................................................59 12.0 Interrupts....................................................................................................................................................................................65 13.0 Direct Memory Access Controller...............................................................................................................................................75 14.0 Power-Down...............................................................................................................................................................................77 15.0 Built-in Self-Test Controller........................................................................................................................................................79 16.0 Electrical Characteristics............................................................................................................................................................83 17.0 Packaging Information................................................................................................................................................................89 Index....................................................................................................................................................................................................95 On-Line Support...................................................................................................................................................................................97 Systems Information and Upgrade Hot Line........................................................................................................................................97 Reader Response................................................................................................................................................................................98 Product Identification System...............................................................................................................................................................99 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: (cid:127) Microchip’s Worldwide Web site; http://www.microchip.com (cid:127) Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. Advance Information DS39662A-page 2  2004 Microchip Technology Inc. ENC28J60 1.0 OVERVIEW The ENC28J60 consists of seven major functional blocks: The ENC28J60 is a stand-alone Ethernet controller 1. An SPI interface that serves as a communica- with an industry standard Serial Peripheral Interface tion channel between the host controller and the (SPI™). It is designed to serve as an Ethernet network ENC28J60. interface for any controller equipped with SPI. 2. Control Registers which are used to control and The ENC28J60 meets all of the IEEE 802.3 specifica- monitor the ENC28J60. tions. It incorporates a number of packet filtering 3. A dual port RAM buffer for received and schemes to limit incoming packets. It also provides an transmitted data packets. internal DMA module for fast data throughput and hard- ware assisted IP checksum calculations. Communica- 4. An arbiter to control the access to the RAM tion with the host controller is implemented via two buffer when requests are made from DMA, interrupt pins and the SPI, with data rates of up to transmit and receive blocks. 10Mb/s. Two dedicated pins are used for LED link and 5. The bus interface that interprets data and network activity indication. commands received via the SPI interface. A simple block diagram of the ENC28J60 is shown in 6. The MAC (Medium Access Control) module that Figure1-1. A typical application circuit using the device implements IEEE 802.3 compliant MAC logic. is shown in Figure1-2. With the ENC28J60, two pulse 7. The PHY (Physical Layer) module that encodes transformers and a few passive components are all that and decodes the analog data that is present on is required to connect a microcontroller to a 10Mbps the twisted pair interface. Ethernet network. The device also contains other support blocks, such as the oscillator, on-chip voltage regulator, level translators to provide 5V tolerant I/Os and system control logic. FIGURE 1-1: ENC28J60 BLOCK DIAGRAM LEDA Buffer RX LEDB 8 Kbytes Dual Port RAM MAC RXBM TPOUT+ RXF (Filter) RMII TX TPOUT- ch0 Interface CLKOUT DMA & Control Arbiter ch0 IP Checksum Registers PHY TPIN+ ch1 TX ch1 RX TPIN- TXBM INT Flow Control WOL Bus Interface MIIM RBIAS Interface Host Interface CS(1) SI(1) OSC1 SO SPI System Control PoRweesre-ton RVeoglutalagteor O2s5c iMllaHtzor OSC2 SCK(1) RESET(1) VCAP Note1: These pins are 5V tolerant. Advance Information  2004 Microchip Technology Inc. DS39662A-page 3 ENC28J60 FIGURE 1-2: TYPICAL ENC28J60-BASED INTERFACE MCU ENC28J60 TPIN+/- CS RJ45 I/O SI TPOUT+/- SDO SO SDI ETHERNET SCK SCK TX/RX MAC PHY TRANSFORMER Buffer INT, WOL LEDA INTX LEDB TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name SPDIP, Type Type Description QFN SOIC, SSOP VCAP 1 25 P — 2.5V output from internal regulator. A 10µF capacitor to VSSTX must be placed on this pin. VSS 2 26 P — Ground reference. CLKOUT 3 27 O — Programmable clock output pin.(1) INT 4 28 O — INT interrupt output pin.(2) WOL 5 1 O — Wake-up on LAN interrupt out pin.(2) SO 6 2 O — Data out pin for SPI™ interface.(2) SI 7 3 I ST Data in pin for SPI interface.(3) SCK 8 4 I ST Clock in pin for SPI interface.(3) CS 9 5 I ST Chip select input pin for SPI interface.(3,4) RESET 10 6 I ST Active-low device Reset input.(3, 4) VSSRX 11 7 P — Ground reference for PHY RX. TPIN- 12 8 I ANA Differential signal input. TPIN+ 13 9 I ANA Differential signal input. RBIAS 14 10 I ANA Bias current pin for PHY. Must be tied to VSSRX through a 2kΩ, 1% resistor. VDDTX 15 11 P — Positive supply for PHY TX. TPOUT- 16 12 O — Differential signal output. TPOUT+ 17 13 O — Differential signal output. VSSTX 18 14 P — Ground reference for PHY TX. VDDRX 19 15 P — Positive 3.3V supply for PHY RX. VDDPLL 20 16 P — Positive 3.3V supply for PHY PLL. VSSPLL 21 17 P — Ground reference for PHY PLL. VSSOSC 22 18 P — Ground reference for oscillator. OSC1 23 19 I DIG Oscillator input. OSC2 24 20 O — Oscillator output. VDDOSC 25 21 P — Positive 3.3V supply for oscillator. LEDB 26 22 O — LEDB driver pin.(5) LEDA 27 23 O — LEDA driver pin.(5) VDD 28 24 P — Positive 3.3V supply. Legend: I = Input, O = Output, P = Power, DIG = Digital input, ANA = Analog signal input, ST = Schmitt Trigger Note 1: Pins have a maximum current capacity of 8mA. 2: Pins have a maximum current capacity of 4mA. 3: Pins are 5V tolerant. 4: Pins have an internal weak pull-up to VDD. 5: Pins have a maximum current capacity of 12mA. Advance Information DS39662A-page 4  2004 Microchip Technology Inc. ENC28J60 2.0 EXTERNAL CONNECTIONS 2.2 Oscillator Start-up Timer The ENC28J60 contains an Oscillator Start-up Timer 2.1 Oscillator (OST) to ensure that the oscillator and integrated PHY have stabilized before use. The OST does not expire The ENC28J60 is designed to operate at 25MHz with until 7500 OSC1 clock cycles (300µs) pass after a crystal connected to the OSC1 and OSC2 pins. The Power-on Reset or wake-up from Power-Down mode ENC28J60 design requires the use of a parallel cut occurs. During the delay, all Ethernet registers and crystal. Use of a series cut crystal may give a frequency buffer memory may still be read and written to through out of the crystal manufacturer specifications. A typical the SPI bus. However, software should not attempt to oscillator circuit is shown in Figure2-1. transmit any packets (set ECON1.TXRTS), enable The ENC28J60 may also be driven by an external clock reception of packets (set ECON1.RXEN) or access any source connected to the OSC1 pin as shown in MAC, MII or PHY registers during this period. Figure2-2. When the OST expires, the CLKRDY bit in the ESTAT register will be set. The application software should poll FIGURE 2-1: CRYSTAL OSCILLATOR this bit as necessary to determine when normal device OPERATION operation can begin. ENC28J60 Note: After a Power-on Reset, or the ENC28J60 is removed from Power-Down mode, the OSC1 CLKRDY bit must be polled before C1 To Internal Logic transmitting packets, enabling packet reception or accessing any MAC, MII or XTAL PHY registers. RF(2) RS(1) C2 OSC2 Note 1: A series resistor, RS, may be required for AT strip cut crystals. 2: The feedback resistor, RF, is typically in the range of 2 to 10MΩ. FIGURE 2-2: EXTERNAL CLOCK SOURCE(1) ENC28J60 3.3V Clock from OSC1 External System Open(2) OSC2 Note 1: Duty cycle restrictions must be observed. 2: A resistor to ground may be used to reduce system noise. This may increase system current. Advance Information  2004 Microchip Technology Inc. DS39662A-page 5 ENC28J60 2.3 CLKOUT Pin value). Additionally, Power-Down mode may be entered and the CLKOUT function will continue to The clock out pin is provided to the system designer for operate. When Power-Down mode is cancelled, the use as the host controller clock or as a clock source for OST will be reset but the CLKOUT function will other devices in the system. The CLKOUT has an continue. When the CLKOUT function is disabled internal prescaler which can divide the output by 1, 2, (ECOCON = 0), the CLKOUT pin is driven low. 3, 4 or 8. The CLKOUT function is enabled and the The CLKOUT function is designed to ensure that mini- prescaler is selected via the ECOCON register mum timings are preserved when the CLKOUT pin (Register2-1). function is enabled, disabled or the prescaler value is To create a clean clock signal, the CLKOUT pin is held changed. No high or low pulses will be outputted which low for a period when power is first applied. After the exceed the frequency specified by the ECOCON Power-on Reset ends, the OST will begin counting. configuration. However, when switching frequencies, a When the OST expires, the CLKOUT pin will begin out- delay between two and eight OSC1 clock periods will putting its default frequency of 6.25MHz (main clock occur where no clock pulses will be produced (see divided by 4). At any future time that the ENC28J60 is Figure2-3). During this period, CLKOUT will be held reset by software or the RESET pin, the CLKOUT func- low. tion will not be altered (ECOCON will not change FIGURE 2-3: CLKOUT TRANSITION ECOCON 80 ns to 320 ns Delay Changed REGISTER 2-1: ECOCON: CLOCK OUTPUT CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — COCON2 COCON1 COCON0 bit 7 bit 0 bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 COCON2:COCON0: Clock Output Configuration bits 111 = Reserved for factory test. Do not use. Glitch prevention not assured. 110 = Reserved for factory test. Do not use. Glitch prevention not assured. 101 = CLKOUT outputs main clock divided by 8 (3.125 MHz) 100 = CLKOUT outputs main clock divided by 4 (6.25 MHz) 011 = CLKOUT outputs main clock divided by 3 (8.333333 MHz) 010 = CLKOUT outputs main clock divided by 2 (12.5 MHz) 001 = CLKOUT outputs main clock divided by 1 (25 MHz) 000 = CLKOUT is disabled. The pin is driven low. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Advance Information DS39662A-page 6  2004 Microchip Technology Inc. ENC28J60 2.4 Magnetics, Termination and Other Some of the digital circuitry in the ENC28J60 operates External Components at a nominal 2.5V to reduce power consumption. A 2.5V regulator is incorporated internally to generate the To complete the Ethernet interface, the ENC28J60 necessary voltage. The only external component requires several standard components to be installed required is a 10µF capacitor for stability purposes. This externally. These components should be connected as capacitor should be attached from VCAP to ground. The shown in Figure2-4. internal regulator was not designed to drive external On the differential receive pins (TPIN+/TPIN-), a loads. 1:1pulse transformer rated for 10BASE-T operation is All power supply pins must be externally connected to required. On the differential transmit pins the same 3.3V power source. Similarly, all ground (TPOUT+/TPOUT-), a 1:1 pulse transformer with a references should be externally connected to the same center tap is required. The transformers should be ground node. Each VDD and VSS pin pair should have rated for isolation of 2kV or more to protect against a 0.1µF ceramic bypass capacitor placed as close to static voltages. See Section16.0 “Electrical Charac- the pins as possible. Relatively high currents are nec- teristics” for specific transformer requirements. Both essary to operate the twisted pair interface, so all wires portions additionally require two 50Ω, 1% resistors and should be kept as short as possible and reasonable a 0.01µF capacitor for proper termination. wire widths should be used on power wires to reduce resistive loss. The internal analog circuitry in the ENC28J60 requires that an external 2kΩ, 1% resistor be attached from RBIAS to ground. FIGURE 2-4: EXTERNAL CONNECTIONS 3.3V RJ-45 TPOUT+ 50Ω Ferrite 1 1% Bead(1) I/O CS 2 SCK SCK 50Ω 0.01µF SDO SI 1% SDI SO TPOUT- 1:1 CT 3 TPIN+ MCU 5.0V ← 3.3V ENC28J60 50Ω 4 Level 1% 5 LoSghicif(t2) 510%Ω 0.01µF 1:1 TPIN- 6 INT0 INT INT1 WOL 7 VCAP LEDA LEDB RBIAS 8 2K 10µF 1% .001µF 2kV Note 1: Ferrite Bead should be rated for at least 100mA. 2: Required only if the microcontroller is operating at 5V. Advance Information  2004 Microchip Technology Inc. DS39662A-page 7 ENC28J60 2.5 I/O Levels 2.6 LED Configuration The ENC28J60 is a 3.3V part; however, it was The LEDA and LEDB pins support automatic polarity designed to be easily integrated into 5V systems. The detection on Reset. The LEDs can be connected such SPI CS, SCK and SI inputs, as well as the RESET pin, that the pin must source current to turn the LED on, or are all 5V tolerant. On the other hand, if the host alternately connected such that the pin must sink cur- controller is operated at 5V, it quite likely will not be rent to turn the LED on. Upon system Reset, the within specifications when its SPI and interrupt inputs ENC28J60 will detect how the LED is connected and are driven by the 3.3V CMOS outputs on the begin driving the LED to the default state configured by ENC28J60. A unidirectional level translator would be the PHLCON register. If the LED polarity is changed necessary. while the ENC28J60 is operating, the new polarity will not be detected until the next system Reset occurs. An economical 74HCT08 (quad AND gate), 74ACT125 (quad 3-state buffer) or many other 5V CMOS chips LEDB is unique in that the connection of the LED is with TTL level input buffers may be used to provide the automatically read on Reset and determines how to ini- necessary level shifting. The use of 3-state buffers tialize the PHCON1.PDPXMD bit. If the pin sources permits easy integration into systems which share the current to illuminate the LED, the bit is cleared on SPI bus with other devices. Figure2-5 and Figure2-6 Reset and the PHY defaults to half-duplex operation. If show example translation schemes. the pin sinks current to illuminate the LED, the bit is set on Reset and the PHY defaults to full-duplex operation. FIGURE 2-5: LEVEL SHIFTING USING Figure2-7 shows the two available options. If no LED AND GATES is attached to the LEDB pin, the PDPXMD bit will reset to an indeterminate value. MCU ENC28J60 FIGURE 2-7: LEDB POLARITY AND RESET CONFIGURATION I/O CS OPTIONS SCK SCK SO SI Full-Duplex Operation: +3.3V PDPXMD = 1 SI SO OSC1 CLKOUT INT0 INT LEDB INT1 WOL Half-Duplex Operation: FIGURE 2-6: LEVEL SHIFTING USING PDPXMD = 0 3-STATE BUFFERS LEDB MCU ENC28J60 I/O CS SCK SCK SO SI SI SO OSC1 CLKOUT INT0 INT INT1 WOL Advance Information DS39662A-page 8  2004 Microchip Technology Inc.