En variabel bit lengde 9-bit 50MS/S SAR ADC Jørgen Moe Sandvik Master i elektronikk Innlevert: Desember 2012 Hovedveileder: Trond Ytterdal, IET Norges teknisk-naturvitenskapelige universitet Institutt for elektronikk og telekommunikasjon Master Thesis Circuit and system design A Variable Bit Length 9-bit 50MS/s SAR ADC by Jørgen Moe Sandvik Supervisor Trond Ytterdal Report delivered: 27.12.2012 Faculty of information technology, mathematics and electrical engineering Norwegian university of science and technology A Variable Bit Length 9-Bit 50MS/s SAR ADC i Abstract A 9-bit 50MS/s SAR ADC with a simulated power consumption of 24.5 µW was designed for this thesis. Specifications were made for application with in-probe electronic as part of an ultrasound system. A novel switching-scheme-employingvariablebitlengthencod- ing – was introduced in order to simplify successive ap- proximation. Pre-layout results reported a FoM of just 1.37 fJ/conversion step, which is favorable to all pub- lished designs to date. Recenttechnologyadvancementshasseentheultrasound fieldexpandingintohandheldmarkets[33]. Morepower efficient solutions, in addition to existing enhanced res- olution 3-D technology both place strict requirements for analog/mixed-signal design. Composite electronics within the probe casing - allowing close-to-source signal processing - is believed to be the future of ultrasound devices. ADC designs suitable for in-probe technology requireultralowpowerandnoisecharacteristicstowards supporting multiple channels on a single SoC. Excellent performance of recent SAR ADCs make them a viable alternative for in-probe technology [2, 7, 12, 4]. WorkinthisthesisshowtheflexibilityoftheSARalgo- rithm. The relatively simple implementation/decoding oftheVBLapproach,complimentedbytheaccuracyde- pendency of the level detection range makes the ADC reconfigurable by digital signal processing. Recentpublisheddesignhasreportedrelativelylowpower consumption for the comparator [15, 7]. A motivation forthethesiswastoseewhethermultipleoperatedcom- parators could reduce power in remaining circuitry. Im- ii plementation of a level-detector - supporting the VBL switching-scheme - has lead to improvements in: Power efficiency, speed and metastability-induced errors. The device consists of two comparators operated in parallel, with a relative DC-offset generated by difference in the capacitiveload. Decisionpointsofthecomparatorsshift with DC-offset, and are atoned for a range desired by the modified SAR algorithm. Anextensiveliterarysearchofrecentmethodologiesand resultswasconducted,andasummerypresentingstate- of-the-art designs is included with the work. An ap- proach using no external references where chosen as a basisfor theDAC design. Emphasizewasmade oncon- stantcommon-modevoltagesuitablyforcomparatorde- sign eliminating pre-amplifiers or buffers. Digitallogicconsistingofserialconnectedbitslicesusing a novel differential approach is proposed. Level detec- tor outputs are connected to the digital logic switching only a portion of transistors in the bitslice during con- version. Trade-offbetweenswitchingactivityandcircuit area proves effective, with only 12.5% of overall power consumed in the digital part. Powersimulationsreportedthelevel-detectorasthedom- inant source of consumption, thereby being subject to furtheroptimizationwithregardstopower. Nonetheless aproof-of-concept8-bitADCimplementation-operated with the novel switching-scheme - produced 8.96 ENOB while dissipating less power. , iii Contents 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . 1 1.2 Ultrasound Application . . . . . . . . . . . . . . 3 1.3 Major Contributions . . . . . . . . . . . . . . . . 4 1.4 Outline . . . . . . . . . . . . . . . . . . . . . . . 5 2 Theory 7 2.1 General . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Power Consumption . . . . . . . . . . . . 7 2.1.2 Noise . . . . . . . . . . . . . . . . . . . . 15 2.1.3 Signal-to-Noise/Distortion Ratio . . . . . 22 2.1.4 Scalar Quantization . . . . . . . . . . . . 24 2.2 Performance of Data Converters . . . . . . . . . 26 2.2.1 Quatnization Noise . . . . . . . . . . . . . 26 2.2.2 Effective Number of Bits. . . . . . . . . . 29 2.2.3 Bandwidth . . . . . . . . . . . . . . . . . 30 2.2.4 Non-Linearity . . . . . . . . . . . . . . . . 32 2.2.5 Figure-of-Merit . . . . . . . . . . . . . . . 32 2.3 Comparator . . . . . . . . . . . . . . . . . . . . . 33 2.4 Digital Logic . . . . . . . . . . . . . . . . . . . . 37 2.5 Sampling Switch . . . . . . . . . . . . . . . . . . 38 2.6 Digital-to-Analog Converter . . . . . . . . . . . . 40 2.7 DAC Noise Modeling . . . . . . . . . . . . . . . . 40 2.8 Capacitor Mismatch Error . . . . . . . . . . . . . 44 iv 3 Previous State-of-the-Art 45 3.1 Top-Plate Sampling . . . . . . . . . . . . . . . . 46 3.2 Differential input . . . . . . . . . . . . . . . . . . 48 3.3 Monotonic Decreasing Switching Scheme . . . . . 50 3.4 Merged Capacitor Switching . . . . . . . . . . . . 50 4 Proposed 51 4.1 Stable Common-mode Switching Scheme . . . . . 51 4.2 Variable Bit Length . . . . . . . . . . . . . . . . 58 4.3 Level Detector . . . . . . . . . . . . . . . . . . . 68 4.4 Decoding the VBL Code . . . . . . . . . . . . . . 69 4.5 Digital Logic . . . . . . . . . . . . . . . . . . . . 71 5 Design 76 5.1 Digital Logic . . . . . . . . . . . . . . . . . . . . 76 5.2 Digital-to-Analog Converter . . . . . . . . . . . . 77 5.3 Bootstrap switch . . . . . . . . . . . . . . . . . . 79 5.4 Level Detector . . . . . . . . . . . . . . . . . . . 83 6 Results 87 6.1 Specifications . . . . . . . . . . . . . . . . . . . . 87 6.2 Overview of Main Simulated Results . . . . . . . 87 6.3 Power . . . . . . . . . . . . . . . . . . . . . . . . 87 6.4 Noise . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.5 Non-Linearity . . . . . . . . . . . . . . . . . . . . 88 6.6 Deadzone . . . . . . . . . . . . . . . . . . . . . . 91 7 Discussion 91 7.1 General Comments to Simulated Results . . . . . 92 v 7.2 Impact of Design Choices . . . . . . . . . . . . . 93 7.3 Reconfigurability of the Design . . . . . . . . . . 95 7.4 Metastability in the Level-Detector . . . . . . . . 96 7.5 PossibleImplementationwithCommunicationSys- tems . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.6 Comparison to Previous State-of-the-Art Designs 103 8 Conclusion 105 List of Figures 1 A typical fron-end for an ultrasound system . . . 3 2 Technology Roadmap for number of transistors vs. gate length . . . . . . . . . . . . . . . . . . . 8 3 Transistor-level inverter with parasitic load . . . 10 4 Resistor Noise Models . . . . . . . . . . . . . . . 17 5 Noise model for a capacitor in parallel with a re- sistor . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Model of a SC circuit. . . . . . . . . . . . . . . . 20 7 Noise model for a MOSFET . . . . . . . . . . . . 23 8 Embedded Quantization . . . . . . . . . . . . . . 25 9 Quantizationlevelsasafunctionoftheinputsignal 27 10 Quantization error for a 4-bit data converter . . 29 11 Effective Resolution Bandwidth . . . . . . . . . . 31 12 Track-and-latch stage . . . . . . . . . . . . . . . 34 13 Block diagram of SAR ADC digital logic . . . . . 37 14 On-resistance for MOS-transistors . . . . . . . . 38 15 A unipolar capacitive charge-redistribution DAC 41 vi 16 Equivalencapacitanceseenfromthesamplinswitch 42 17 A single-ended charge-redistribution DAC with inverters . . . . . . . . . . . . . . . . . . . . . . . 47 18 An equivalent circuit for a capacitor with para- sitic capacitances . . . . . . . . . . . . . . . . . . 47 19 Differential Charge-Redistrubution DAC . . . . . 49 20 Split potential capacitors . . . . . . . . . . . . . 52 21 Switchin Schemes . . . . . . . . . . . . . . . . . . 54 22 Differential split potential capacitor array . . . . 56 23 Differential split potential capacitor array with asymmetrical LSB . . . . . . . . . . . . . . . . . 58 24 Switchin Schemes . . . . . . . . . . . . . . . . . . 59 25 Decision levels in a segment of the quantization error for a 4-bit ADC . . . . . . . . . . . . . . . 62 26 Level detection in the VBL switching scheme . . 65 27 Differential split potential capacitor array with variable bit length code . . . . . . . . . . . . . . 67 28 Syntax for decoding VBL output . . . . . . . . . 70 29 Bitslice schematic . . . . . . . . . . . . . . . . . . 72 30 Select waveforms of the bitslice . . . . . . . . . . 73 31 Block diagram for the Digital Logic. . . . . . . . 76 32 Digital-to-Analog Converter . . . . . . . . . . . . 78 33 Bootstrap switch . . . . . . . . . . . . . . . . . . 80 34 Bootstrap waveform . . . . . . . . . . . . . . . . 81 35 Implementation of a level detector . . . . . . . . 84 36 Non-linearity analysis . . . . . . . . . . . . . . . 90 37 Deadzone Sweep . . . . . . . . . . . . . . . . . . 92 38 Metastability in the level detector . . . . . . . . 97 39 Variable length code . . . . . . . . . . . . . . . . 99 vii