Development of Phase Change Memory Cell Electrical Circuit Model for Non-volatile Multistate Memory Device Nemat Hassan Ahmed ElHassan, BSc. Thesis submitted to the University of Nottingham for the degree of Doctor of Philosophy January 2017 Abstract Phase change memory (PCM) is an emerging non-volatile memory technology that demonstrates promising performance characteristics. The presented research aims to study the feasibility of using resistive non-volatile PCM in embedded memory applications, and in bridging the performance gap in traditional memory hierarchy between volatile and non-volatile memories. The research studies the operation dynamics of PCM, including its electrical, thermal and physical properties; in order to determine its behaviour. A PCM cell circuit model is designed and simulated with the aid of SPICE tools (LTSPICE IV). The first step in the modelling process was to design a single-level PCM (SLPCM) cell circuit model that stores a single bit of data. To design the PCM circuit model; crystallization theory and heat transfer equation were utilized. The developed electrical circuit model evaluates the physical transformations that a PCM cell undergoes in response to an input pulse. Furthermore, the developed model accurately simulated the temperature profile, the crystalline fraction, and the resistance of the cell as a function of the programming pulse. The circuit model is then upgraded into a multilevel phase change memory (MLPCM) cell circuit model. The upgraded MLPCM circuit model stores two bits of data, and incorporates resistance drift with time. The multiple resistance levels were achieved by controlling the programming pulse width in the range of 10ns to 200ns. Additionally, the drift behaviour was precisely evaluated; by using statistical data of drift exponents, and evaluating the exact drift duration. Moreover, the simulation results for the designed SLPCM and MLPCM cell models were found to be in close agreement with experimental data. The simulated I- I V characteristics for both SLPCM and MLPCM mimicked the experimentally produced I-V curves. Furthermore, the simulated drift resistance levels matched the experimental data for drift durations up to 103 seconds; which is the available experimental data duration in technical literature. Furthermore, the simulation results of MLPCM showed that the deviation between the programmed and drifted resistance can reach 6x106Ω in less than 1010 seconds. This resistance deviation leads to reading failures in less than 100 seconds after programming, if standard fixed sensing thresholds method was used. Therefore, to overcome drift reliability issues, and retain the density advantage offered by multilevel operation; a time-aware sensing scheme is developed. The designed sensing scheme compensates for the drift caused resistance deviation; by using statistical data of drift coefficients to forecast adaptive sensing thresholds. The simulation results showed that the use of adaptive time-aware sensing thresholds completely eliminated drift reliability issues and read errors. Furthermore, PCM based nanocrossbar memory structure performance in terms of delay and energy consumption is studied in simulation environment. The nanocrossbar is constructed with a grid of connecting wires; and the designed PCM cell circuit model is used as memory element and placed at junction points of the grid. Then the effect of connecting nanowires resistance in PCM nanocrossbar performance is studied in passive crossbars. The resistance of a connecting wire segment was evaluated with physical formulas that calculate nanoscaled conductors’ resistance. Then a resistor that is equivalent to each wire segment resistance is placed in the tested crossbar structure. Simulation results showed that due to connecting wires resistance; the PCM cells are not truly biased to programming voltage and ground. This leads to 40% deviation II in the programed low resistive state from the targeted levels. Thus, affecting PCM reliability and decreasing the high to low resistance ratio by 90%. Therefore, programming and architectural solutions to wire resistance related reliability issue are presented. Where dissipated power across wire resistance is compensated for; by controlling programming pulse duration. The programming solution retained reliability however; it increased programming energy consumption and delay by an average of 40pJ and 60ns respectively per operation. Additionally, the effects of leakage energy in PCM based nanocrossbars were studied in simulation environment. Then, a structural solution was developed and designed. In the designed structure; leakage sneak paths are eliminated by introducing individual word lines to each memory element. This method led to 30% reduction in reading delay, and consumed only about sixth the leakage energy consumed by the standard structure. Moreover, a sensing scheme that aims to reduce energy consumption in PCM based nanocrossbars during reading process was explored. The sensing method is developed using AC current in contrast to the standard DC current reading circuits. In the designed sensing circuit, a low pass filter is utilized. Accordingly, the filter attenuation of the applied AC reading signal indicates the stored state. The proposed circuit design of the AC sensing scheme was constructed and studied in simulation environment. Simulation results showed that AC sensing has reduced reading energy consumption by over 50%; compared to standard DC sensing scheme. Furthermore, the use of SLPCM and MLPCM in memory applications as crossbar memory elements, and in logic applications i.e. PCM based LUTs was explored and tested in simulation environment. The PCM performance in crossbar memory was then compared to current Static Random Access Memory (SRAM) III technology and against one of the main emerging resistive non-volatile memory technologies i.e. Memristors. Simulation results showed that programming and reading energy consumption of PCM based crossbars were five orders of magnitude more than SRAM based crossbars. And reading delay of SRAM based crossbars was only 38% of reading delay of PCM based counterparts. However, PCM cells occupies less than 60% of the area required by SRAM and can store multiple bit in a single cell. Moreover, Memristor based nanocrossbars outperformed PCM based ones; in terms of delay and energy consumption. With PCM consuming 2 orders of magnitude more energy during programming and reading. PCM also required 10 times the programming delay. However, PCM crossbars offered higher switching resistance range i.e. 170kΩ compared to the 20kΩ offered by memristors; which support PCM multibit storage capability and higher density. IV Acknowledgment Thank God for all his blessings. My guidance comes from him. In him I trust and unto him I turn. My sincere thanks go to Dr. Nandha Kumar, my supervisor for his patience, motivation, and guidance that helped me in all the time of research and writing of this thesis. My deep gratitude goes to my advisor Prof. Haider Abbas, for his continuous support and giving me the opportunity to peruse my Ph.D. study. Thanks to my dear parents Hassan Ahmed ElHassan & Zubaida Mohammed Ali for being my biggest supporters and critics, and standing by me through my life. Their unlimited love gave me strength and determination. Finally, I would like to thank everyone who helped and supported me throughout my research. V List of Publications Conference Proceedings 1. Nemat H. El-Hassan, T. Nandha Kumar, and Haider Abbas F. Almurib, “Improved SPICE Model for Phase Change Memory Cell”, IEEE 5th International Conference on Intelligent and Advanced Systems ICIAS, Kuala Lumpur, Malaysia, June 2014. (Shortlisted for the Best Presenter Award) DOI: 10.1109/ICIAS.2014.6869529) 2. Ong Ming Hong, Nemat H. El-Hassan, T. Nandha Kumar, and Haider Abbas F. Almurib, “A Novel Emulator Design for Phase Change Memory”, IEEE 2nd International Conference on Electronic Design, Penang, Malaysia, August 2014. DOI: 10.1109/ICED.2014.7015779 3. Nemat H. El-Hassan, T. Nandha Kumar, and Haider Abbas F. Almurib, “Multilevel Phase Change Memory Cell Model”, IEEE Asia Pacific Conference on Circuits and Systems, Okinawa, Japan, November 2014. DOI: 10.1109/APCCAS.2014.7032822 4. Patrick W. C. Ho, Nemat H. El-Hassan, T. Nandha Kumar, and Haider Abbas F. Almurib, “PCM and Memristor Based Nanocrossbars,” IEEE International Conference on Nanotechnology, Rome, Italy, July, 2015. DOI: 10.1109/NANO.2015.7388636 5. Nemat H. El-Hassan, M. R. Ahmed Shahad, T. Nandha Kumar, and Haider Abbas F. Almurib, “AC Sense Circuit for Memristor Based Memory Crossbar”, IEEE student conference on research and development, Kuala Lumpur, Malaysia , December 2015. DOI: 10.1109/SCORED.2015.7449367 6. Nemat H. El-Hassan, T. Nandha Kumar, and Haider Abbas F. Almurib, “Performance study of Phase Change Memory in Different Crossbar Architectures,” The International Nanotech and Nanoscience Conference and Exhibition, Paris, June 2015. VI Refereed Journals 1. Nemat H. El-Hassan, T. Nandha Kumar, and Haider Abbas F. Almurib, “Time-Aware Multilevel Phase Change Memory Cell”, Elsevier Microelectronic Journal, Vol. 56, pp. 74–80, October 2016. http://dx.doi.org/10.1016/j.mejo.2016.08.007 2. Nemat H. El-Hassan, T. Nandha Kumar, and Haider Abbas F. Almurib, “Wire Resistance Effect in PCM Based Nanocrossbar Array,” IET Journal of Engineering, 2016. DOI: 10.1049/joe.2016.0212 3. Nemat H. El-Hassan, Ong Ming Hong, T. Nandha Kumar, and Haider Abbas F. Almurib, “Phase Change Memory Cell Emulator Circuit Design”, Elsevier Microelectronic Journal, 2016. VII Table of Contents Abstract I Acknowledgment V List of Publications VI Table of Contents VIII List of Figures XI List of Tables XVI Glossary I CHAPTER 1 2 Introduction 1.1 Background 2 1.2 Aims 5 1.3 Objectives 5 1.4 Contribution of the research 6 1.5 Thesis outline 7 CHAPTER 2 10 Preliminaries 2.1 Overview 10 2.2 Memory Performance Characteristics 10 2.3 Traditional memory hierarchy 12 2.3.1 SRAM 13 2.3.2 DRAM 13 2.3.3 Flash memory 13 2.4 Emerging resistive NVM 15 2.4.1 Resistive RAM (ReRAM) “Memristor” 16 2.4.2 Phase change memory (PCM) 16 2.4.3 Magnetic Tunnel Junction (MTJ) 17 2.4.4 Emerging NVMs performance comparison 18 2.5 PCM characteristics 19 2.5.1 Materials 19 2.5.2 Operating principles of PCM 21 VIII 2.5.3 Crystallization of PCM 30 2.5.4 PCM device optimization 37 2.5.5 Reliability issues of PCM 40 2.6 Summary 42 CHAPTER 3 44 Literature Review 3.1 Overview 44 3.2 PCM modelling review 44 3.2.1 SLPCM modelling in literature 46 3.2.2 MLPCM modelling in literature 47 3.3 Drift phenomenon in amorphous phase 49 3.3.1 Drift origins 49 3.3.2 Drift mitigation in literature 51 3.4 Crossbars 52 3.4.1 Performance issues in crossbars 54 3.4.2 Connecting wires resistance 54 3.4.3 Leakage currents 57 3.5 Methodology 60 3.5.1 PCM cell and memory crossbar design flow chart 60 3.5.2 Design process 61 3.5.3 Testing and verification 61 3.6 Summary 62 CHAPTER 4 65 PCM Electrical Circuit Modelling 4.1 Overview 65 4.2 PCM cell model design 65 4.2.1 SLPCM cell model description 68 4.2.2 MLPCM cell model upgrade 75 4.3 Simulation results 77 4.3.1 SLPCM simulation results and discussion 77 4.3.2 MLPCM simulation results and discussion 88 4.4 Drift mitigation by time-aware sensing 93 4.4.1 Proposed time-aware sensing 94 4.4.2 Time-aware sensing implementation 96 4.4.3 Simulation results 97 IX