DISTRIBUTED AMPLIFIER CIRCUIT DESIGN USING A COMMERCIAL CMOS PROCESS TECHNOLOGY by Kyle Gene Ross A thesis submitted in partial fulfillment of the requirements of the degree of Master in Science in Electrical Engineering MONTANA STATE UNIVERSITY Bozeman, Montana July 2006 © COPYRIGHT by Kyle Gene Ross 2006 All Rights Reserved ii APPROVAL of a thesis submitted by Kyle Gene Ross This thesis has been read by each member of the thesis committee and has been found to be satisfactory regarding content, English usage, format, citations, bibliographic style, and consistency, and is ready for submission to the Division of Graduate Education. James P. Becker Approved for the Department of Electrical and Computer Engineering James N. Peterson Approved for the Division of Graduate Education Joseph J. Fedock iii STATEMENT OF PERMISSION OF USE In presenting this thesis in partial fulfillment of the requirements for a master's degree at Montana State University, I agree that the Library shall make it available to borrowers under rules of the Library. If I have indicated my intention to copyright this thesis by including a copyright notice page, copying is allowable in so far as the copyright license grants without express permission from the copyright holder. Any of these conditions may be waived with permission from the copyright holder. Kyle Gene Ross July 2006 iv ACKNOWLEDGEMENTS I would like to express my gratitude to those who without their help and encouragement this project would not have been a success. First, I would like to thank my advisor Dr. James Becker for his support and guidance throughout my undergraduate and graduate career. His enthusiasm for research and teaching has inspired me to strive for the same. Secondly, I would like to thank committee members Dr. Donald Thelen and Andy Olson for their indispensable advice and patience. Also, this work would not have been nearly as great without the relief provided by fellow lab-mates Edward Dickman and Kyle Lyson. Lastly, I would like to acknowledge the support provided for this work by both the National Science Foundation (NSF) under grant #347469 and the MOSIS Service through the MOSIS Educational Program (MEP). v TABLE OF CONTENTS 1. INTRODUCTION...........................................................................................................1 Introduction.....................................................................................................................1 Thesis Overview..............................................................................................................2 2. DISTRIBUTED AMPLIFIERS.......................................................................................4 Background.....................................................................................................................4 Theory of Operation........................................................................................................5 MOSFET Realization of the DA.....................................................................................8 Design Procedures.........................................................................................................18 CMOS Figures of Merit.........................................................................................18 Device Sizing Procedures......................................................................................20 3. CMOS TRANSMISSION LINE REALIZATION........................................................29 Transmission Line Parameters......................................................................................29 Coplanar Strip-line (CPS) Selection and Design..........................................................30 Optimal Device Quantity Deduction.............................................................................41 4. BIASING AND PLANAR INDUCTOR DESIGN.......................................................42 Distributed Amplifier Biasing.......................................................................................42 Planar Spiral Inductor Design.......................................................................................45 Inductor Figures of Merit.......................................................................................47 Planar Spiral Inductor Implementation..................................................................51 5. CALIBRATION AND CHARACTERIZATION.........................................................53 Introduction...................................................................................................................53 Calibration.....................................................................................................................54 Short-Open-Load-Thru (SOLT).............................................................................56 Thru-Reflect-Line (TRL).......................................................................................58 Measurements................................................................................................................63 Delay Line Validation............................................................................................63 Square Planar Spiral Inductors...............................................................................66 Isolated Transistors................................................................................................69 Distributed Amplifier.............................................................................................76 6. CONCLUSIONS AND RECOMMENDATIONS FOR FURTHER WORK...............81 Summary.......................................................................................................................81 Recommendations for Further Research.......................................................................82 Planar Spiral Inductors...........................................................................................82 Planar Microwave Circuit Design Course.............................................................83 REFERENCES CITED......................................................................................................84 vi TABLE OF CONTENTS - CONTINUED APPENDICES...................................................................................................................88 APPENDIX A: Non-Quasistatic Effects...............................................................89 APPENDIX B: AMIS C5 BSIM3v3 SPICE Model Parameters...........................92 APPENDIX C: MOSIS T5AR Run Wafer Electrical Test Data and SPICE Model Parameters......................................................................................93 APPENDIX D: IE3D Extracted RLGC Parameters for 500mm, 50Ω CPS..........98 APPENDIX E: Analytical Planar Spiral Inductor Design...................................100 vii LIST OF TABLES Table Page 3.1 DC parasitic parameter values of a 200µm x 0.6µm (WxL) NMOS transistor.....................................................................................................30 3.2 AMIS C5 process specifications for metal layer 3....................................35 3.3 IE3D extracted RLGC parameters for a 500µm, 50Ω CPS.......................36 3.4 Parasitic parameter values of a 200µm x 0.6µm (WxL) NMOS transistor at 1GHz......................................................................................37 3.5 IE3D extracted RLGC parameters for 500µm gate and drain CPS...........38 4.1 Coefficients for modified Wheeler expression..........................................49 4.2 Coefficients for current sheet expression...................................................49 viii LIST OF FIGURES Figure Page 2.1 TWA illustration of the DA.........................................................................6 2.2 Schematic representation of a N-stage MOSFET TWA..............................8 2.3 Lumped-element equivalent circuit for an incremental length of transmission line........................................................................................10 2.4 Small-signal model of the MOSFET when the source is connected to the substrate (body)....................................................................................10 2.5 Small-signal model of the MOSFET after applying Miller's Theorem.....11 2.6 Distributed amplifier transmission line circuits for the (a) gate line and (b) the drain line.........................................................................................11 2.7 Equivalent circuit for single unit cell of (a) gate and (b) drain line circuits........................................................................................................12 2.8 ADS simulation schematic used in determining maximum unit cell electrical lengths........................................................................................13 2.9 CMOS performance envelope as a function of transistor speeds...............21 2.10 Plot illustrating the relationship between a normal, or Gaussian, process distribution and the standard deviation (sigma) limits...............................22 2.11 Unity-gain frequency of 200x0.6 µm (WxL) NMOS transistor (I = 31.1mA)............................................................................................23 D 2.12 ADS simulation setup used to determine unity-gain frequency of NMOS........................................................................................................24 2.13 Source and load stability contours of a single 200µm by 0.6µm (WxL) MOSFET....................................................................................................27 2.14 Source and load stability contours of a single 200µm by 0.6µm (WxL) MOSFET loaded at the gate with a series resistance of 1Ω.......................27 3.1 Microstrip transmission line realized in CMOS substrate using the highest (yellow) and lowest (red) metal interconnect layers.....................31 ix LIST OF FIGURES – CONTINUED Figure Page 3.2 AMIS C5 process family substrate diagram...............................................32 3.3 Coplanar waveguide cross-sectional illustration........................................33 3.4 Coplanar stripline cross-sectional illustration............................................34 3.5 Micrograph of the fabricated gate and drain CPS......................................40 4.1 DA circuit with DC bias network realized with square-spiral inductors...43 4.2 ADS schematic of DA circuit with an optimal DC bias network realized with ideal RF-chokes....................................................................44 4.3 Planar spiral inductor geometries for (a) square, (b) hexagonal, (c) octagonal, and (d) circular realizations......................................................47 5.1 GGB model 40A CPS RF probe tip diagram.............................................54 5.2 Measured 2-port S-parameters of a CS-8 thru line after SOLT calibration..................................................................................................57 5.3 Measured reflection from a CS-8 short circuit after SOLT calibration.....58 5.4 Micrograph of the fabricated CPS TRL calibration standards; TOP-open reflects, MIDDLE-short reflects, BOTTOM-thru line.............60 5.5 Two-port S-parameters of an on-chip thru line after TRL calibration.......62 5.6 Input impedances of on-chip short and open reflects after TRL calibration..................................................................................................63 5.7 Micrograph of an isolated drain delay line being probed after SOLT calibration..................................................................................................64 5.8 ADS delay line phase difference simulation schematic.............................64 5.9 Delay line phase difference, ADS simulation (Si N passivation layer.....65 3 4