Digital-to-Analog Conversion in High Resolution Audio by Ivar Løkken September 2008 Submitted to the Norwegian University of Science and Technology in partial fulfilment of the requirements for the degree philosophiae doctor NTNU Norwegian University of Science and Technology Thesis for the degree philosophiae doctor Faculty of Information Technology, Mathematics and Electrical Engineering Department of Electronics and Telecommunications © Ivar Løkken ISBN 978-82-471-1209-0 [printed version] ISBN 978-82-471-1210-6 [electronic version] ISSN 1503-8181 NTNU Doctoral Theses 2008:257 Printed by NTNU-trykk Abstract This thesis describes theoretical and simulation-based work on digital-to-analog conversion for high resolution audio. The emphasis of the work has been exploration and clarification of issues of contention in previous art. The work has resulted in five scientific papers published in international peer-reviewed journals and conference proceedings, and these papers constitute the main contribution. The papers are included as appendixes, whereas the preceding monograph serves to provide the necessary background for understanding the results, and also their relevance in an audio context. It should be noted that although the research primarily treats DA conversion, the findings and conclusions are largely transferable also to AD conversion since audio ADC performance is often limited by its usually compulsory feedback DAC. The first paper, published in the Journal of the Audio Engineering Society, explores power modulation of the quantization error and the need for dithering in delta-sigma modulators. There has been a lot of dispute on this issue; previous publications having both argued that the DSM is self-dithering and that it has the same dither requirements as a regular REQ. By exploring noise power modulation in the baseband it is shown that even high order DSMs are not self-dithering in the true sense, but that the adverse effects of quantization are reduced when the loop filter is of high order. If the REQ is multi-bit the noise power modulation can be made negligible compared to any practical levels of circuit noise. The second paper, published in IEEE Transactions on Circuits and Systems Part II, explores a class of DSM called non-overloading or NOL modulators. Designing the DSM to be NOL is the only known way to guarantee stability for high order loops, and also the only way to guarantee no quantization noise power modulation. The paper proves that NOL design criteria are equivalent for OF and EF modulators, repudiating a claim of difference in a previous publication, and also their equivalence for rounding and truncating quantizers. Although the results are developed for a certain class of modulators, the methods are easily generalized to any DSM design. It is found desirable to use a many-bit REQ since a NOL DSM with good input swing is then allowed. The third paper, presented at the 31st Conference of the Audio Engineering Society, shows a useful utilization of the results developed in the second paper. Using a many-bit DSM is desirable for several reasons, but will in straightforward implementation require a DEM network of excessive complexity. A previously proposed method to circumvent this is to segment the DAC and DEM using a dedicated Segmentation-DSM. Previous art has used SDSMs with a FIR loop filter to ensure no DAC saturation, restricting the concept to very non-optimal designs. This publication utilizes the NOL method to design IIR SDSMs with significantly improved performance. The fourth paper, submitted to Analog Integrated Circuits and Signal Processing, describes the development of simplified estimates for DSM DAC errors. The mathematical treatment of high order DSMs is exceedingly difficult, but simplifications and rules of thumb have been developed that enable design engineers to make quite straightforward optimization of relevant DSM parameters. A major drawback is that these approximations do not account for analog error sources in the DAC and may therefore lead to unfortunate design choices. This paper explores how common DAC errors depend on the DSM transfer function, and presents extensions of known approximation methods to also include the impact the DSM has on DAC waveform distortion. Again it is confirmed that using a many-bit DSM is advantageous, and also that a conservative DSM design will make the DAC less susceptible to errors. i ii Abstract The fifth and last paper, presented at the 124th Convention of the Audio Engineering Society, utilizes the methods presented in the fourth paper to optimize a DAC with regards to jitter noise. Clock jitter is one of the most critical performance bottlenecks in high resolution audio, and the paper proposes ways to minimize the DAC’s jitter susceptibility. The simplified approximation methods are employed and extended to show that a semidigital FIR DAC gives a more benign output waveform than a segmented DEM DAC of comparable complexity, and that it will be a preferable solution if jitter dominates the error budget. A simple method is also shown to estimate effects of implementation inaccuracies in the analog filter coefficients. Preface This thesis is submitted in partial fulfilment of the requirements for the degree Philosophiae Doctor (Ph.D.) at the Norwegian University of Science and Technology (NTNU), Department of Electronics and Telecommunications. The work has been funded by the Norwegian Research Council under grant 162101 SPECK. My main supervisor has been Professor Trond Sæther and my co-supervisor has been Dr.Ing. Bjørnar Hernes. The studies have been carried out in the period from January 2005 to May 2008. The work includes the equivalent of a little over half a year of full-time course studies (39 ECTS credits), teaching one fifth year master level course on data converters and supervising two students on their master projects. The first year and a half was spent at the university, and after this the work was carried out at the Nordic Semiconductor data converter department. When the Nordic data converter business was acquired by Chipidea Microelectronica, we were two Ph.D. students enrolled at the department who joined in on the move. Chipidea Norway sadly turned out to be a short lived venture, as irreconcilably different visions for the future between the mother company and the Norwegian department staff, eventually led to all regular employees in Norway leaving in order to pursue a fresh start with new company Arctic Silicon Devices. I and the other Ph.D. student were still allowed to finish our studies at the university where I am now, while remaining on Chipidea contracts. So in many ways the circle seems complete, as I am now finishing this study more than three years later, back where it started. iii Acknowledgements This thesis is dedicated to my friends and family, in particular my parents and my sister. If it wasn’t for you, I would not have been here today. As I am sitting in my office at the university writing this, spring is in the air and almost four years have passed since I was in a similar situation as a master student. Then too Trond was my supervisor and in our meetings, which often slanted into hi-fi talks since we are both devout audiophiles and music fans, he aired the idea of doing a Ph.D. on audio conversion. With my background and interests I found this to be an extremely exciting opportunity and jumped at it, and it was arranged between the university, Nordic and the research council to initiate a project. Four years later I have no regrets, as I have learned a lot and met many interesting people on the way. I would like to express my gratitude to those who have been of help; both professionally and administratively, during the years spent pursuing this degree. First and foremost my colleague and fellow Ph.D. student Anders Vinje, who has travelled the same slightly bumpy path to this point as me, has been of tremendous aid during the work on my papers and as a general “sparring partner” during problem solving. His mathematical prowess easily surpasses mine and I would have had a lot more troubled times in front of the notebook if it wasn’t for him. Hurdles related to our somewhat unusual work situation have also been easier to climb than if I had been in it alone. I am also in debt to my main supervisor Trond and co-supervisor Bjørnar, who have been of great help administratively. The path on which I set out is one they were both familiar with from when they did their own Ph.D. degrees, and they helped me to keep my focus on the light in the end of the tunnel even when at times the tunnel itself seemed dark. To spend one and a half years with the former Nordic data converter team gave a sobering insight into the practical aspects of integrated circuit design. Listening in on their project meetings provided a pragmatic context to my theoretical work and helped me maintain a meaningful focus. Thanks to Morten Dammen, Terje Granum, Øystein Moldsvor, Christian Holdø, Håvard Korsvoll, Frode Telstø, Terje Andersen, and Atle Briskemyr for providing an informal and positive work environment with a lot of expertise. Johnny Bjørnsen who remained at Nordic after the takeover also deserves mention as part of this group. Managing a master level course on data converters and advising two master students on their projects was invaluable in learning to communicate and share my knowledge. I thank Lasse Olsen and Florian Bousquet for being interested and skilful students. I also want to thank the staff and students at the NTNU Circuits and Systems group for my time and discussions with them, in particular Prof. Trond Ytterdal, Carsten Wulff, and Rune Kaald. And last but not least; thank you to the management at Chipidea and Prof. João Vital for allowing me and Anders to finish our degrees even though the data converter team fell apart. I am sorry the endeavour of Chipidea Norway ended the way it did. Finally, I would like to pay a small homage to the late audio-guru Steen Aage Duelund, with whom I got to discuss and learn from just before he untimely went away. Although his fields of expertise were only tangentially related to mine, his clairvoyance and ability to think outside the box, his holistic philosophical approach to the art of audio, and his great enthusiasm provided me with a lot of inspiration. His presence is missed. Trondheim, May 2008 Ivar Løkken. iv Table of Contents Abstract.................................................................................................................i Preface.................................................................................................................iii Acknowledgements.............................................................................................iv Table of Contents.................................................................................................v List of Figures....................................................................................................vii List of Abbreviations..........................................................................................ix Chapter 1 Introduction.....................................................................................1 1.1 Hearing and Audio Quality .....................................................................1 1.2 A Brief Historical Review of Digital Audio ...........................................2 1.3 Organization of This Thesis....................................................................4 Chapter 2 Fundamental Theory......................................................................7 2.1 Sampling and Reconstruction..................................................................7 2.2 Quantization...........................................................................................12 2.3 Oversampling.........................................................................................16 2.4 Dither.....................................................................................................17 2.5 Delta-Sigma Modulation.......................................................................19 2.6 The DAC................................................................................................21 2.7 DAC Errors............................................................................................24 Chapter 3 The Delta-Sigma Modulator........................................................35 3.1 Delta Sigma Modulator Design.............................................................35 3.2 Alternative Delta-Sigma Structures.......................................................40 3.3 Stability..................................................................................................43 3.4 Cyclic Behaviour, Tones and Noise Power Modulation.......................46 3.5 Non-Overloading Delta-Sigma Modulators..........................................50 Chapter 4 Mismatch Shaping ........................................................................53 4.1 Mismatch Error Randomization............................................................53 4.2 Element Rotation Techniques................................................................54 4.3 Other Techniques...................................................................................58 4.4 Segmented Mismatch Shaping..............................................................62 Chapter 5 Delta-Sigma and Dynamic DAC Errors.....................................65 5.1 Delta-Sigma and Jitter Error Estimation...............................................65 5.2 Delta-Sigma and Switching Error Estimation.......................................68 5.3 Techniques for Reducing Dynamic Errors............................................73 v vi Table of Contents Chapter 6 Conclusions and Further Work...................................................83 6.1 Conclusions ...........................................................................................83 6.2 Proposals for Further Work...................................................................85 Appendix 1 Frequency Analysis ....................................................................87 Appendix 2 Paper I .........................................................................................91 Appendix 3 Paper I Errata...........................................................................107 Appendix 4 Paper II......................................................................................109 Appendix 5 Paper III....................................................................................115 Appendix 6 Paper IV.....................................................................................121 Appendix 7 Paper V......................................................................................137 Bibliography.....................................................................................................151 List of Figures Figure 1: Equal loudness contours (ISO226).............................................................................1 Figure 2: A-weighting function (IEC/CD 1672)........................................................................2 Figure 3: Digital audio recording and playback chain...............................................................3 Figure 4: Conceptualization of simultaneous masking..............................................................4 Figure 5: Sampling of a continuous-time signal........................................................................7 Figure 6: a) Continuous spectrum b) Sampled spectrum c) Alias distortion.............................8 Figure 7: Sampled waveform of fig.5 and an alias....................................................................9 Figure 8: Conceptual ADC and AAF.........................................................................................9 Figure 9: Conceptual DAC and RCF.......................................................................................10 Figure 10: Output waveform from PCM DAC........................................................................11 Figure 11: Hold reconstruction filtering effect........................................................................12 Figure 12: Uniform scalar mid-thread quantizer......................................................................13 Figure 13: Quantizer input PDF (a) and output PDF (b)..........................................................14 Figure 14: DAC oversampling in the time and frequency domains.........................................17 Figure 15: Oversampling DA-converter with REQ.................................................................17 Figure 16: Dithered quantization..............................................................................................18 Figure 17: First two error moments as function of input level.................................................19 Figure 18: Basic delta-sigma modulator..................................................................................20 Figure 19: Illustration of DSM noise shaping..........................................................................20 Figure 20: Processing gain of modN DSM..............................................................................21 Figure 21: Resistor ladder type DAC.......................................................................................22 Figure 22: DCT integrator SC DAC........................................................................................23 Figure 23: Current mode DAC with external I-V conversion..................................................23 Figure 24: Jitter error in the time domain................................................................................26 Figure 25: Jitter distortion from sinusoid, white and pink jitter...............................................28 Figure 26: Generalized schematic of binary encoded DAC.....................................................29 Figure 27: Generalized schematic of thermometer encoded DAC..........................................29 Figure 28: DAC transfer function, ideal and with INL............................................................30 Figure 29: DAC element on and off switching and error waveform.......................................31 Figure 30: Equivalent small signal circuit for current steering DAC......................................32 Figure 31: INL from finite output impedance..........................................................................33 Figure 32: Basic delta-sigma modulator..................................................................................35 Figure 33: The Silva-Steensgaard modified DSM structure....................................................36 Figure 34: Generalized DSM structure....................................................................................36 Figure 35: Basic modN distributed feedback DSM.................................................................37 Figure 36: Generalized distributed feedback DSM..................................................................37 Figure 37: Distributed feedback DSM with resonator for NTF optimization..........................38 Figure 38: Optimization of NTF zeros.....................................................................................39 Figure 39: Distributed feed-forward DSM structure................................................................39 Figure 40: The error-feedback DSM structure.........................................................................40 Figure 41: A two-stage MASH modulator...............................................................................41 Figure 42: Principle for the “ultimate modulator”...................................................................42 Figure 43: Trellis noise shaping modulator..............................................................................43 Figure 44: Example of instability in high order DSM.............................................................44 Figure 45: Modified linear DSM model used in Root Locus method......................................45 Figure 46: Processing gain with 1-bit stable DSM..................................................................46 Figure 47: Output spectrum from fifth order DSM with rational DC input.............................47 vii viii List of Figures Figure 48: Input PDF (a) and output PDF (b), single-bit quantizer.........................................49 Figure 49: DAC element randomization, B=3 bit example.....................................................53 Figure 50: DWA DAC element rotation, B=3 bit example......................................................55 Figure 51: Element selection sequence with DWA.................................................................55 Figure 52: Element selection sequence with second order DWA............................................58 Figure 53: Switching sequence for each element in a 3-bit DSM DAC..................................59 Figure 54: Switching sequence for each element in a 3-bit DSM DAC with DWA................59 Figure 55: Two element swapper cell......................................................................................60 Figure 56: Swapping cell network for DEM, B=3...................................................................60 Figure 57: Data splitting and reduction for tree structure DEM..............................................61 Figure 58: Complete reduction tree with first order mismatch shaping...................................62 Figure 59: DEM and DAC segmentation.................................................................................62 Figure 60: Equivalent signal flow diagram of segmented DAC..............................................63 Figure 61: DEM and DAC segmentation with SDSM.............................................................63 Figure 62: Two time DEM and DAC segmentation................................................................64 Figure 63: Area error model for jitter distortion analysis........................................................65 Figure 64: SJNR example, 50ps white jitter........................................................................67 max Figure 65: Jittered spectrum with a) sinusoid, b) white, and c) mixed jitter............................68 Figure 66: Simulated spectrum, 10ps switching asymmetry....................................................69 Figure 67: Simulated SSNR example, 10ps switching asymmetry.....................................70 max Figure 68: Simulated ISI error spectrum..................................................................................70 Figure 69: Simulated spectrum, 10ps switching asymmetry, DWA........................................71 Figure 70: Simulated spectrum of LPCM DAC with DWA....................................................72 Figure 71: Simulated spectrum, 10ps switching asymmetry, R2DWA...................................72 Figure 72: Return-to-zero waveform........................................................................................73 Figure 73: SJNR 50ps white jitter and RZ DAC.................................................................75 max, Figure 74: Dual-RZ waveform.................................................................................................76 Figure 75: DAC time-interleaving, a) functional diagram, b) waveform................................76 Figure 76: 1-bit DSM REQ with semidigital filtering DAC for multi-level output................77 Figure 77: Multi-bit DSM REQ with semidigital filtering DAC.............................................78 Figure 78: a) Analog PWM modulation b) Digital PCM-PWM conversion...........................79 Figure 79: UPWM error...........................................................................................................80 Figure 80: PWM-based algorithm used by Reefman et al. to eliminate mismatch and ISI.....81 Figure 81: Illustration of DFT spectral leakage.......................................................................88 Figure 82: Spectrum of sine multiplied with rectangular (top) and hann (bottom) window...89 Figure 83: Convoluted spectrum and DFT samples with coherent sampling..........................90 Figure 84: Illustration of signal leakage and noise leakage impairing DSM DFT..................90