Freescale Semiconductor Document Number: AN3599 Rev.0, 07/2008 Application Note Digital Signal Processing and ADC/DAC for DSP56800/E by: XiangJun Rong Systems and Applications Engineering Asia/Pacific Region 1 Introduction Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 The DSP56800/E is Freescale’s 16-bit fixed-point digital 2 DSP56800/E Features. . . . . . . . . . . . . . . . . . . . . . . . . . . 2 signal controller (DSC), which can be used in a variety 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 On-Chip ADC Features. . . . . . . . . . . . . . . . . . . . . . 3 of industrial control applications, such as motor control 2.3 ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 4 for BLDC, PMSM, ACIM, SR, and STEP motors, as 2.4 How to Calculate ENOB . . . . . . . . . . . . . . . . . . . . . 5 2.5 ADC Voltage Reference Circuit. . . . . . . . . . . . . . . . 8 well as in switch-mode power supplies and as an 3 Filter Design Using QEDesign Lite . . . . . . . . . . . . . . . . . 9 electronic lamp ballast. 3.1 FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 IIR Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Freescale devices that use the DSP56800/E core can 3.3 Illustration of the Coefficients from QEDesign Lite 21 3.4 How to Call the IIR API Function. . . . . . . . . . . . . . 24 perform up to 32–120 MIPS. 3.5 Modify the Link Command File for Dynamic Memory • The DSP56F80x can perform up to 40 MIPS Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 How to Call the FIR API Function . . . . . . . . . . . . . 31 • The MC56F83xx can perform up to 60 MIPS 4 FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1 FFT Implementation . . . . . . . . . . . . . . . . . . . . . . . 35 • The MC56F80xx can perform up to 32 MIPS 4.2 FFT Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 • The DSP5685x can perform up to 120 MIPS 4.3 General Code to Compute DFT for Comparison. . 39 5 DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1 DAC of the MC56F802x Family. . . . . . . . . . . . . . . 40 Most of the devices have on-chip flash, GPIO, watchdog 5.2 Class D Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . 42 timer, Quad Timer, ADC, DAC, CAN bus, SPI bus, SCI 6 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 bus, IIC bus, decoder, and JTAG/OnCE peripherals. AppendixA IIR Filter Code . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AppendixB References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 This application note provides: • On-chip ADC specifications of the DSP56800/E ©Freescale Semiconductor, Inc., 2008. All rights reserved. DSP56800/E Features • Procedures to design a finite impulse response filter (FIR) and an infinite impulse response filter (IIR) using CodeWarrior embedded QEDesign Lite for the DSP56800/E • Examples by Processor Expert (PE) to create a digital filter and FFT based on the DSP56800/E core • The relationship between PWM cycle and PWM resolution when the PWM is viewed as a DAC Figure 1 is a common digital signal processing procedure. The ADC and DAC can be on-chip or off-chip. The DSC is capable of implementing the digital signal processing in real time based on the DSP architecture and compact instructions set. Most of the Freescale DSCs have on-chip ADC. Low-Pass Sampler and Digital-to-Analog Reconstruction Anti-Aliasing Analog-to-Digital DSP Operation Converter Low Pass Filter Converter FIR Filter N Σ c(k) × (n-k) A/D D/A k=0 x(t) y(t) x(n) Finite Impulse y(n) Response Analog In Analog Out A Ideal n ai Filter G f f c Frequency A Analog n ai Filter G f f c Frequency A Digital n ai Filter G f f c Frequency AA004 Figure1. Digital Signal Processing Scheme 2 DSP56800/E Features 2.1 Overview Every device in the DSP56800/E family is a general-purpose DSC for various control and signal processing applications. Digital Signal Processing and ADC/DAC for DSP56800/E, Rev.0 2 Freescale Semiconductor DSP56800/E Features As shown in Figure 1, the key attributes of the DSP core are: • Multiply/accumulate (MAC) operation in one clock • Harvard structure, fetching up to two operands per instruction cycle, for the MAC • Program control to provide versatile operation • Input/output transferring data to and from the DSC The Freescale DSP56F80x family is well suited for digital signal processing and motor control. It combines a DSP’s calculation capability with an MCU’s controller features on a single chip. DSP56F805, a typical member of the DSP56F80x family, provides these peripheral blocks: • Two pulse-width modulator modules (PWMA and PWMB). Each provides six PWM outputs, three current-sense inputs, and four fault inputs. It has fault-tolerant design with dead-time insertion and supports both center-aligned and edge-aligned modes. • A 12-bit analog-to-digital convertor (ADC). Supports two simultaneous conversions with dual 4-pin multiplexed inputs. The ADC can be synchronized by a PWM or by a timer. • Two quadrature decoders (Quad Dec0 and Quad Dec1). Each provides four inputs or two additional Quad Timers, A and B. • Two dedicated general-purpose Quad Timers totalling six pins: Timer C with two pins and Timer D with four pins. • CAN 2.0 A/B module with 2-pin ports used to transmit and receive • Two serial communication interfaces (SCI0 and SCI1). Each provides two pins, or four additional GPIO lines. • Serial peripheral interface (SPI) with configurable 4-pin port, or four additional GPIO lines. • Computer-operating-properly (COP) watchdog timer. • Two dedicated external interrupt pins. • 14 dedicated general-purpose I/O (GPIO) pins and 18 multiplexed GPIO pins. • External reset pin for hardware reset. • JTAG/On-chip emulation (OnCE). • Software-programmable, phase-lock loop-based frequency synthesizer for the DSP core clock. Other than the fast analog-to-digital converter and 16-bit quadrature timers, the pulse-width modulation block (PWM) offers a high degree of freedom in its configuration to control various motors in an efficient way. 2.2 On-Chip ADC Features The ADC module has these features: • 12-bit resolution • A sampling rate up to 1.66 million samples per second • Maximum ADC clock frequency of 5 MHz with 200 ns period • Single conversion time of 8.5 ADC clock cycles (8.5 × 200 ns = 1.7 μs) • Additional conversion time of 6 ADC clock cycles (6 × 200 ns = 1.2 μs) Digital Signal Processing and ADC/DAC for DSP56800/E, Rev.0 Freescale Semiconductor 3 DSP56800/E Features • Eight conversions in 26.5 ADC clock cycles (26.5 × 200 ns = 5.3 μs) using simultaneous mode • Simultaneous or sequential sampling • Internal multiplexer to select two of eight inputs • Ability to sequentially scan and store up to eight measurements • Ability to simultaneously sample and hold two inputs • Optional interrupts at end of scan, if an out-of-range limit is exceeded or if at zero crossing • Optional sample correction by subtracting a pre-programmed offset value • Signed or unsigned result • Single-ended or differential inputs In loop mode, the time between each conversion is six ADC clock cycles (1.2 μs). Using simultaneous conversion, two samples can be obtained in 1.2 μs. Therefore the module can process up to 1.6 million samples per second. The external analog signal must be sampled in a constant cycle if FIR, IIR, or FFT is adopted. The DSP56800/E family provides two trigger modes to acquire samples. One is software trigger mode, which is set by setting the START bit in the ADC control register; the other is hardware trigger mode. In hardware trigger mode, the timer outputs a signal to trigger the ADC internally. The user can set the timer register to set up a constant sample cycle. The DSP56800/E also supports a more complicated trigger mode. For example, the PWM reload event triggers the timer and the timer triggers the ADC after delays. This is an important mode for sampling three motor phase currents for a Clark transformation. Refer to the application note AN1933, Synchronization of On-chip Analog to Digital Converter on DSP56F80x DSPs, for details. Only the hardware trigger mode can guarantee the synchronization of the ADC samples, so the user must use the hardware trigger mode to get samples via on-chip ADC to implement FIR, IIR, or FFT. 2.3 ADC Specifications This section defines all the ADC specifications used in this application note. • Differential non-linearity (DNL) — the measurement of the maximum deviation from the ideal step size of 1 LSB. • Effective number of bits (ENOB or effective bits) — another method of specifying signal-to-noise and distortion (SINAD). ENOB is defined as (SINAD – 1.76)/6.02, and it is equivalent to the number of bits in a perfect ADC. • Gain error — the deviation from the ideal slope of the transfer function. • Integral non-linearity (INL) — a measurement of the deviation of each individual code from a line drawn from ground (1/2 LSB below the first code transition) through positive full scale (1/2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the bottom of that code value or ground. • Offset voltage — the maximum input voltage of the ADC analog channel when the ADC sample reading is zero. Digital Signal Processing and ADC/DAC for DSP56800/E, Rev.0 4 Freescale Semiconductor DSP56800/E Features • Signal-to-noise ratio (SNR) — the ratio, expressed in dB, of the RMS value of the fundamental signal to the RMS value of the sum of all other spectral components below one-half of the sampling frequency, but not including harmonics from f2 to f9 or DC. • Signal-to-noise plus distortion (S/N+D or SINAD) — the ratio, expressed in dB, of the RMS value of the fundamental signal to the RMS value of all the other spectral components below half of the sample frequency, including all harmonics but excluding DC. • Spurious free dynamic range (SFDR) — the ratio, expressed in dB, of the RMS values of the fundamental signal to the RMS value of the peak spurious signal. The spurious signal is any signal presented in the output spectrum that is not presented at the input. • Total harmonic distortion (THD) — the ratio, expressed in dB, of the RMS value of the fundamental signal to the RMS value of the total of the first nine harmonics. THD is calculated with f1 as the RMS power of the fundamental (output) frequency and f2 through f10 as the RMS power in the first nine harmonic frequencies. • Crosstalk between channels — the mutual influence between two analog channels expressed in dB. For example, the crosstalk between two ADC analog channels is 60 dB in the MC56F8300 family. If the input of one channel is 1 V, the second channel may get 1 mV noise signal from the first channel. • Common mode voltage — defined only in the ADC differential input mode, and equal to the average voltage of the two differential input signals. Note that each channel voltage must range from GND to V even in differential mode, because the on-chip ADC of the DSP56800/E cannot refh accept negative voltage. • V current — the current the V pin consumes. When the user uses a voltage reference, this refh refh specification must be considered. • Impedance of the analog channel — refer to Freescale application note AN1947, DSP56F800 ADC, for the formula to compute this value. It is about 200 kΩ. NOTE The root mean square (RMS) for a collection of n values {x ,x ,x ,...,x } 1 2 3 n N 1 2 can be expressed as x = ---- ∑ x , for a sine signal. If the rms N i i=1 amplitude of the sine signal is A, the RMS of the sine signal is . A 2 2.4 How to Calculate ENOB Resolution is an important specification for an ADC. It indicates the minimum ADC recognition for the analog input variation. For example, if the ADC is 12 bits, the resolution of the ADC is 12 bits. But because the actual ADC cannot recognize the analog input variation as its resolution describes, we define the ENOB parameter to describe its actual resolution. 2.4.1 How to Derive the ENOB Parameter From a mathematical point of view, quantization is the process of mapping the continuous analog signal to a discrete definite number set. Quantization error is introduced in the process. We can use the Digital Signal Processing and ADC/DAC for DSP56800/E, Rev.0 Freescale Semiconductor 5 DSP56800/E Features quantization error to measure the difference between the actual analog value x(k) and the corresponding ADC digital sample. Assume the digital ADC sample is xˆ(k) = b ×211 +b ×210 + …+b × 20 Eqn.1 11 10 0 We use the root-mean-square error to define the quantization error as Equation2. The error x is the difference between the analog sample and the digital sample: x= x(k)–xˆ(k) Eqn.2 For a general ADC, we assume the analog signal voltage is uniformly distributed. Therefore the uniform quantization is the optimum quantization. Suppose that: • Analog signal ranges from –V to +V • Nominal resolution is L bits • Desired number of levels is 2L • Quantization gap is 2 × V/2L • Sample frequency is F s • Signal frequency is F (for meeting the Nyquist sampling theorem, F must be greater than 2F) s Suppose we quantize a sine waveform signal with the ADC — the amplitude of the sine signal is V. In an ideal ADC converter, the quantization error is uniformly distributed between –1/2 LSB and +1/2 LSB. The sum of the noise, or the root-mean-square quantization error (or the energy of the quantization error), is Δ⁄2 2 Δ⁄2 2 1 1 3 Δ⁄2 Δ2 J= ∫ x × P(x)dx= ∫ x × ---dx= -------x = ------ Δ 3Δ –Δ⁄2 12 –Δ⁄2 –Δ⁄2 Eqn.3 In the above formula, x denotes the quantization error between the continuous analog signal and the digital sample, and p(x) is the possibility of the quantization error assumed to be uniformly distributed. So 1 L p(x)= --- and Δ= 2×V ⁄2 Δ and the noise energy is 2 V J= ----------------- Eqn.4 2L 3×2 For a sine signal with amplitude V, the signal energy is V2/2, so 10 × log (Signal Energy/Noise Energy) = 10 × log ((V2/2)/J) = 6.02L + 1.76 10 10 Eqn.5 Digital Signal Processing and ADC/DAC for DSP56800/E, Rev.0 6 Freescale Semiconductor DSP56800/E Features ENOB L = [10 × log (Signal Energy/Noise Energy) – 1.76] / 6.02 10 Eqn.6 2.4.2 One Method to Compute ENOB Parameter According to Equation6, if we can calculate the signal and noise energy, we can derive L. L is the ENOB in the data sheet. Suppose we input an arbitrary initial-phase sine signal to the ADC, which can be expressed as 2 2 Asin(wt)+Bcos(wt). The amplitude of the sine signal is A +B . Assume that the frequency of the signal 2 2 is F and the signal energy is (A + B )⁄ 2. Assume that the sample frequency is F . Select the input REQ S sine signal frequency F to make the result of F /F to be an integer, such as 100, to increase REQ S REQ accuracy. Assume we get one whole cycle sine discrete signal y(k) by sampling the sine signal. The number of points is NP, which equals F /F . Use Equation7 to calculate the noise value. S REQ NP–1 2πk 2πk 2 J= ∑ y(k) –A × sin--------- –B× cos--------- Eqn.7 NP NP k= 0 Estimate the optimum values for parameters A and B that will yield a minimum value for the noise energyJ. After calculating the optimum A and B, we can compute J. Let the following partial derivatives with respect to A and B equal zero. ∂J ------= 0 ∂A ∂J ------= 0 ∂B To calculate signal energy, we use Equation8 and Equation9, where parameter k is from 0 to NP–1. ⎛2πk⎞ ⎛2πk⎞ 2πk ∑ y(k) –Asin --------- –Bcos --------- × sin---------= 0 Eqn.8 ⎝NP⎠ ⎝NP⎠ NP ⎛2πk⎞ ⎛2πk⎞ 2πk ∑ y(k) –Asin --------- –Bcos --------- × cos---------= 0 Eqn.9 ⎝NP⎠ ⎝NP⎠ NP Using these two equations, we can calculate A and B. With the values for A and B, use Equation7 to calculate the noise, J. Signal Energy = (A2+B2) / 2 Eqn.10 Note that the average of the y(k) sequence is zero. We can subtract the original sample sequence by the average and get the y(k) sequence. Digital Signal Processing and ADC/DAC for DSP56800/E, Rev.0 Freescale Semiconductor 7 DSP56800/E Features Using Equation6 we can calculate L, which is ENOB as defined in the data sheet. We can also calculate ENOB according to a discrete Fourier transformation (DFT) of the y(k) sequence — they yield the same result. For example, assume we have computed the DFT of the y(k) sequence, and get the power spectrum sequence from bin0 to bin50. Obviously, bin0 is the DC component which is zero here — bin1 is the fundamental component. In computing the SNR, because bin10 to bin50 are regarded as noise, we sum from bin10 to bin50 to get noise. Bin2 to bin10 are regarded as harmonics. In computing S/N+D or SINAD, bin2 to bin50 are regarded as noise. Therefore, to compute the value for the noise, sum from bin2 to bin50. Note that when we compute for all the specifications, the input sine signal voltage must be in full scale. We can use Equation11 to compute the ENOB after we get the SINAD. ENOB = (SINAD – 1.76) / 6.02 Eqn.11 2.5 ADC Voltage Reference Circuit The on-chip ADC of the DSP56800/E has a V pin that can be used to provide reference voltage to the refh ADC. Use a dedicated voltage reference device to improve the ADC precision. Refer to the data sheet of each individual DSP chip to get the typical current requirements of the V pin that provides a reference refh voltage for the on-chip ADC. For example, the V pin of DSP56F805 typically needs 12 mA DC current, ref and the optimum voltage of the V is about 3.0 V. But for the MC56F8300 family and MC56F8000 ref family, the optimum input voltage for the V is 3.3 V. This application note uses the LM385-ADJ chip refh as the voltage reference device for the V pin of DSP56F805. The user can connect the V pin to V refh refh DDA for a low-cost design. 3.3 V R1 V refh + R2 + FB – R3 10 μA – Digital Signal Processing and ADC/DAC for DSP56800/E, Rev.0 8 Freescale Semiconductor Filter Design Using QEDesign Lite Figure2. Voltage Reference Circuit Here, the “+”, “–”, and “FB” are nodes copied from the data sheet of the LM385-ADJ chip. Because the clamp diode clamps the voltage between the FB node and the V node to 1.24 V, and the current flow refh through R2 and R3 is the same, we can derive the formula given here: V –1.24 1.24 ----r--e---f-h------------------= ---------- Eqn.12 R3 R2 ⎛ R3⎞ V = 1.24 1+ ------- Eqn.13 refh ⎝ R2⎠ If R3 is 14.3 kΩ and R2 is 10 kΩ, then V will be 3.0 V. refh R1 must be a tri-port adjustable resistor. The maximum resistance is R1 = 0.3 V / 0.012 A = 25 Ω. It must be less than 25 Ω. Typically it is about 16–17 Ω, because the V pin consumes 12 mA current. refh 3 Filter Design Using QEDesign Lite 3.1 FIR Filter We provide a filter solution, including digital filter design and digital filter implementation, using the DSP. For filter design, CodeWarrior for DSP56800/E integrates QEDesign Lite, which can help the user design an individual filter as required. NOTE QEDesign Lite must be installed in your computer and working normally. This tool is integrated into CodeWarrior. Use the procedure below to design a filter using QEDesign Lite. 1. As shown in Figure 3, click the FIR button in the tool bar, and select filter type in the “FIR (Window) Design” dialog box that appears. The filter types include Lowpass, Highpass, Bandpass, and Bandstop. Click on the Next button. Digital Signal Processing and ADC/DAC for DSP56800/E, Rev.0 Freescale Semiconductor 9 Filter Design Using QEDesign Lite Figure3. QEDesign Lite FIR Filter Type Selection 2. As shown in Figure 4, input filter parameters vary according to the application. In the Lowpass Filter window, passband ripple (dB) is the gain of the filter, a gain that fluctuates with the frequency within the passband frequency field. Stopband ripple (dB) works exactly the same way for the stopband frequency field. If you input x as the passband ripple within the passband, the gain ripple is 10–x/20 within the passband frequency. For example, if you input 3, the filter gain ripple is 0.708. The larger the ripple is in dBs, the smaller the filter gain ripple will be. For a low pass FIR filter design, assume that the sample frequency is 1000 Hz, the passband is 100Hz, the stopband is 200 Hz, the passband ripple is 3 dB (the filter gain fluctuates between 70.7% and 100% of the maximum gain within the passband), and the stopband ripple is 20 dB (the filter gain fluctuates within 10% of the maximum gain within the stopband). You can input these typical values: — Sampling frequency: 1000 — Passband frequency: 100 — Stopband frequency: 200 — Passband ripple (dB): 3 — Stopband ripple (dB): 20 Digital Signal Processing and ADC/DAC for DSP56800/E, Rev.0 10 Freescale Semiconductor