DDDDiiiiggggiiiittttaaaallll IIIInnnntttteeeeggggrrrraaaatttteeeedddd CCCCiiiirrrrccccuuuuiiiittttssss AA DDeessiiggnn PPeerrssppeeccttiivvee Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic AArriitthhmmeettiicc CCiirrccuuiittss January, 2003 MModdiiffiiedd bby GG. BBaccaranii - JJanuary 22000055 1 © Digital Integrated Circuits2nd EE141 Arithmetic Circuits AAAAddddddddeeeerrrrssss 2 © Digital Integrated Circuits2nd EE141 Arithmetic Circuits FFFFuuuullllllll AAAAddddddddeeeerrrr AA BB Full Cin Cout aaddddeerr Sum 3 © Digital Integrated Circuits2nd EE141 Arithmetic Circuits TTTThhhheeee BBBBiiiinnnnaaaarrrryyyy AAAAddddddddeeeerrrr A B Full Cin Cout aaddddeerr Sum SS = AA ⊕⊕ BB ⊕⊕ CC i = ABC + ABC + ABC + ABC ii ii ii ii C = AB + BC + AC o i i 4 © Digital Integrated Circuits2nd EE141 Arithmetic Circuits SSuumm aanndd CCaarrrryyyy aaggggaaiinnsstt PP,,,, GG,,,, KK Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A⊕B Kill (K) = A B = A+B Note that we will be sometimes using an alternate definition for Propagate (P) = A + B 5 © Digital Integrated Circuits2nd EE141 Arithmetic Circuits SSSSuuuummmm aaaannnndddd CCCCaaaarrrrrrrryyyy aaaaggggaaaaiiiinnnnsssstttt PPPP,,,, GGGG,,,, KKKK ⊕ 6 © Digital Integrated Circuits2nd EE141 Arithmetic Circuits CCoommpplliimmeennttaarryy SSttaattiicc CCMMOOSS FFuullll AAddddeerr V DD V DD CC AA BB ii A B A BB B C i V DD A X CC ii S C A i C i AA BB BB VV DD A B C A i C oo BB 2288 TTrraannssiissttoorrss 7 © Digital Integrated Circuits2nd EE141 Arithmetic Circuits AA bbeetttteerr SSttrruuccttuurree:: tthhee MMiirrrroorr AAddddeerr V DD V V A DD DD A B B A B C B i Kill "0"-Propagate A C i C C o S i A C i "1"-Propagate Generate A B B A B C A i B 24 transistors 8 © Digital Integrated Circuits2nd EE141 Arithmetic Circuits MMiirrrroorr AAddddeerr ((SSttiicckk DDiiaaggrraamm)) V DD AA BB CC BB AA CC CC CC AA BB i i o i C o SS GGNNDD 9 © Digital Integrated Circuits2nd EE141 Arithmetic Circuits TThhee MMiirrrroorr AAddddeerr (cid:137) The NMOS and PMOS chains are completely symmetrical; a maximum of two series transistors can be observed in the carry-generation circuitry. (cid:137) When laying out the cell, the most critical issue is the mi- niimiizatiion off thhe capaciitance at nodde CC . TThhe redductiion off o the diffusion capacitances is particularly important. (cid:137)(cid:137) TThhee ccaappaacciittaannccee aatt nnooddee CC iiss ccoommppoosseedd ooff ffoouurr ddiiffffuussiioonn o capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell . (cid:137) The transistors connected to C are placed closest to the i output. (cid:137) OOnly the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size. 10 © Digital Integrated Circuits2nd EE141 Arithmetic Circuits