Digital Electronics 2 (cid:3) Series Editor Robert Baptiste Digital Electronics 2 (cid:3) (cid:3) Sequential and Arithmetic Logic Circuits (cid:3) (cid:3) (cid:3) (cid:3) (cid:3) Tertulien Ndjountche (cid:3) (cid:3) (cid:3) (cid:3) (cid:3) (cid:3) (cid:3) (cid:3) (cid:3) (cid:3) (cid:3) (cid:3) First published 2016 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc. Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may ooly be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address: ISTELtd John Wiley & Sons, Inc. 27-37 StGeorge's Road 111 River Street London SW19 4EU Hoboken, NJ 07030 UK USA www.iste.co.uk www.wiley.com @ISTELtd2016 The rights of Tertulien Ndjountche to be identified as the author of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988. Library of Congress Control Number: 2016945589 British Library Cataloguing-in-Publication Data A CIP record for this book is available from the British Library ISBN 978-1-84821-985-4 Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Chapter1.LatchandFlip-Flop . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.Generaloverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.1.SRlatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.2.SRlatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.3.Application: switchdebouncing . . . . . . . . . . . . . . . . . . . . 11 1.3.GatedSRlatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.1.ImplementationbasedonanSRlatch . . . . . . . . . . . . . . . . . 12 1.3.2.ImplementationbasedonanSRlatch . . . . . . . . . . . . . . . . 14 1.4.GatedDlatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.BasicJKflip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.6.Tflip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.7.Master-slaveandedge-triggeredflip-flop . . . . . . . . . . . . . . . . . 20 1.7.1.Master-slaveflip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.7.2.Edge-triggeredflip-flop . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.8.Flip-flopswithasynchronousinputs . . . . . . . . . . . . . . . . . . . . 30 1.9.Operationalcharacteristicsofflip-flops . . . . . . . . . . . . . . . . . . 33 1.10.Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.11.Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Chapter2.BinaryCounters . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.1.Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.2.Modulo4counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.3.Modulo8counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.Modulo16counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.1.Modulo10counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 vi DigitalElectronics2 2.5.Counterwithparallelload . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.6.Downcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.7.Synchronousreversiblecounter . . . . . . . . . . . . . . . . . . . . . . 64 2.8.Decodingadowncounter . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.9.Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.10.Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Chapter3.ShiftRegister . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.1.Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.2.Serial-inshiftregister . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.3.Parallel-inshiftregister . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.4.Bidirectionalshiftregister . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.5.Registerfile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.6.Shiftregisterbasedcounter . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.6.1.Ringcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.6.2.Johnsoncounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.6.3.Linearfeedbackcounter . . . . . . . . . . . . . . . . . . . . . . . . 94 3.7.Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.8.Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Chapter4.ArithmeticandLogicCircuits . . . . . . . . . . . . . . . . . . 117 4.1.Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.2.Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.2.1.Halfadder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.2.2.Fulladder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.2.3.Ripple-carryadder. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.2.4.Carry-lookaheadadder . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.2.5.Carry-selectadder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.2.6.Carry-skipadder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.4.Arithmeticandlogicunit . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.5.Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.5.1.Multiplierof2-bitunsignednumbers . . . . . . . . . . . . . . . . . 136 4.5.2.Multiplierof4-bitunsignednumbers . . . . . . . . . . . . . . . . . 137 4.5.3.Multiplierforsignednumbers . . . . . . . . . . . . . . . . . . . . . 138 4.6.Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.7.Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.8.Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Chapter5.DigitalIntegratedCircuitTechnology . . . . . . . . . . . . . 177 5.1.Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 5.2.Characteristicsofthetechnologies . . . . . . . . . . . . . . . . . . . . . 177 Contents vii 5.2.1.Supplyvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 5.2.2.Logiclevels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.2.3.Immunitytonoise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.2.4.Propagationdelay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 5.2.5.Electricpowerconsumption . . . . . . . . . . . . . . . . . . . . . . 179 5.2.6.Fan-outorloadfactor . . . . . . . . . . . . . . . . . . . . . . . . . . 179 5.3.TTLlogicfamily. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 5.3.1.Bipolarjunctiontransistor . . . . . . . . . . . . . . . . . . . . . . . 180 5.3.2.TTLNANDgate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 5.3.3.IntegratedTTLcircuit. . . . . . . . . . . . . . . . . . . . . . . . . . 182 5.4.CMOSlogicfamily . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 5.4.1.MOSFETtransistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 5.4.2.CMOSlogicgates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.5.Opendrainlogicgates. . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 5.5.1.Three-statebuffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 5.5.2.CMOSintegratedcircuit . . . . . . . . . . . . . . . . . . . . . . . . 188 5.6.Otherlogicfamilies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 5.7.Interfacingcircuitsofdifferenttechnologies . . . . . . . . . . . . . . . 189 5.8.Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 5.9.Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Chapter6.SemiconductorMemory . . . . . . . . . . . . . . . . . . . . . 195 6.1.Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 6.2.Memoryorganization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 6.3.Operationofamemory . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 6.4.Typesofmemory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.4.1.Non-volatilememory . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.4.2.Volatilememories . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.4.3.Characteristicsofthedifferentmemorytypes . . . . . . . . . . . . 207 6.5.Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.5.1.Memoryorganization . . . . . . . . . . . . . . . . . . . . . . . . . . 208 6.5.2.Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 6.6.Othertypesofmemory . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 6.6.1.FerromagneticRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 220 6.6.2.Content-addressablememory. . . . . . . . . . . . . . . . . . . . . . 222 6.6.3.Sequentialaccessmemory . . . . . . . . . . . . . . . . . . . . . . . 223 6.7.Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.8.Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Chapter7.ProgrammableLogicCircuits . . . . . . . . . . . . . . . . . . 245 7.1.Generaloverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 7.2.Programmablelogicdevice . . . . . . . . . . . . . . . . . . . . . . . . . 246 7.3.Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 viii DigitalElectronics2 7.3.1.Implementationoflogicfunctions . . . . . . . . . . . . . . . . . . . 255 7.3.2.Two-bitadder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 7.3.3.Binary-to-BCDandBCD-to-binaryconverters . . . . . . . . . . . . 263 7.4.Programmablelogiccircuits(CPLDandFPGA) . . . . . . . . . . . . . 263 7.4.1.Principleandtechnology . . . . . . . . . . . . . . . . . . . . . . . . 264 7.4.2.CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 7.4.3.FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 7.5.References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 7.6.Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 7.7.Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Preface The omnipresence of electronic devices in everyday life is accompanied by the size reduction and the ever-increasing complexity of digital circuits. This comprehensive and easy-to-understand work deals with basic principles of digital electronicsandallowsthereadertograspthesubtletiesofdigitalcircuitsfromlogic gates to finite-state machines. It presents all the aspects related to combinational logic and sequential logic. It introduces techniques to establish in a simple and concise manner logic equations, as well as methods for the analysis and design of digital circuits. Emphasis has been especially laid on design approaches that can be used to ensure a reliable operation of finite-state machines. Various programmable logic circuit structures and their applications are also presented. Each chapter includespracticalexamplesandwell-designedexerciseswithworkedsolutions. This series of books discusses all the different aspects of digital electronics, following a descriptive approach combined with a gradual, detailed, and comprehensive presentation of basic concepts. The principles of combinational and sequentiallogicarepresented,aswellastheunderlyingtechniquesfortheanalysisand design of digital circuits. The analysis and design of digital circuits with increasing complexityisfacilitatedbytheuseofabstractionsatthecircuitandarchitecturelevels. Thisworkconsistsofthreevolumesdevotedtothefollowingsubjects: 1)combinationallogiccircuits; 2)sequentialandarithmeticlogiccircuits; 3)finitestatemachines. A progressive approach has been chosen and the chapters are relatively independentofeachother.Tohelpmasterthesubjectmatterandputintopracticethe different concepts and techniques, topics are complemented by a selection of exerciseswithsolutions. x DigitalElectronics2 P.1.Summary Volume2dealswithsequentialcircuitsandarithmeticandlogiccircuits.Thelogic stateoftheoutputofasequentiallogiccircuitcandepend, atanygiventime, onthe inputs but also on the previous logic state of the outputs. Depending on whether a clocksignalisusedtosynchronizetheoutputstatechangeornot,asequentialcircuit issaidtobesynchronousorasynchronous.Arithmeticcircuitscanbeusedtoperform addition,subtraction,multiplicationanddivisionoperationsondigitaldata.Volume2 containsthefollowingsevenchapters: 1)LatchandFlip-flop; 2)BinaryCounters; 3)ShiftRegisters; 4)ArithmeticandLogicCircuits; 5)DigitalIntegratedCircuitTechnology; 6)SemiconductorMemory; 7)ProgrammableLogicCircuits. P.2.Thereader This work is an indispensable tool for all engineering students on a bachelors or masters course who wish to acquire detailed and practical knowledge of digital electronics. It is detailed enough to serve as a reference for electronic, automation andcomputerengineers. TertulienNDJOUNTCHE June2016 1 Latch and Flip-Flop 1.1. Introduction Alatchorflip-flopisabistablecircuitthatismostoftenusedinapplicationsthat requiredatastorage.Itschiefcharacteristicisthattheoutputisnotdependentsolely on the present state of the input but also on the preceding output state. A bistable circuithastwocomplementaryoutputsthatcanassumeeitherofthetwologiclevels 0or1. There are several common types of latches and flip-flops. Latches often have no dedicated input for the clock signal. They can be combined to implement level-triggeredandedge-triggeredflip-flops.Flip-flopscanbetriggeredbyoneofthe levelsoroneoftheedgesofaclocksignal(oradigitalsignal). 1.2. Generaloverview AsimplelatchcanbeimplementedusingtwoNORortwoNANDlogicgates. A NOR gate based latch with initial conditions specified is represented in Figure 1.1(a). The characteristic equation for each of the outputs is determined by assuming that the logic gates have different propagation times1 and this may be modeledasforadelay,Δ,betweenasignalthatbecomesavailableattheoutputand thefeedbacksignalappliedtotheinput.Inthisway, thelogiccircuitofthelatch, as illustrated in Figure 1.1(b), may be transformed as shown in Figures 1.1(c) and1.1(d). 1Propagationdelaysinlogicgatesareassumedtotaketheform1and1+Δ,respectively. Digital Electronics 2: Sequential and Arithmetic Logic Circuits, First Edition. Tertulien Ndjountche. © ISTE Ltd 2016. Published by ISTE Ltd and John Wiley & Sons, Inc.