DESIGN TECHNIQUES AND TRADEOFFS OF FINFET SRAM MEMORIES by MICHAEL ALLEN TURI A dissertation submitted in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY WASHINGTON STATE UNIVERSITY School of Electrical Engineering and Computer Science MAY 2013 © Copyright by MICHAEL ALLEN TURI, 2013 All Rights Reserved © Copyright by MICHAEL ALLEN TURI, 2013 All Rights Reserved To the Faculty of Washington State University: The members of the Committee appointed to examine the dissertation of MICHAEL ALLEN TURI find it satisfactory and recommend that it be accepted. ___________________________________ José G. Delgado-Frias, Ph.D., Chair ___________________________________ Deukhyoun Heo, Ph.D. ___________________________________ Partha P. Pande, Ph.D. ii ACKNOWLEDGEMENTS The research in this dissertation has been supported by the Boeing Centennial Endowed Chair, 2011 IEEE Circuits and Systems Society Pre-doctoral Scholarship #2, School of Electrical Engineering and Computer Science (EECS), and Washington State University (WSU). I wish to extend many thanks for this funding which has made this work possible. This research was conducted in the High Performance Computer Systems (HiPerCopS) group at WSU under the direction of Dr. José Delgado-Frias. I am tremendously appreciative of the guidance and encouragement provided by Dr. Delgado-Frias; his involvement and assistance greatly influenced the research presented in this dissertation. I also appreciate the help and suggestions from the other members of my dissertation committee: Dr. Partha Pande and Dr. Deuk Heo. I also wish to thank Dr. Jabu Nyathi for his help during the early stages of my research and I want to thank Al Guyer for his help with the Linux systems used for this research and for bailing me out when I was having system or network problems. I greatly appreciated the help, camaraderie, and motivation provided by the HiPerCopS group’s graduate students. I wish to thank Jason Van Dyken and Zhe (Nick) Zhang for their friendship and help during the bulk of my research. I thank Johnathan Cree for his friendship and help during my degree and at our internship at IHP-Microelectronics. I also wish to thank Mitch Myjak and Danny Blum for their help during the early stages of my research and my career search. I thank Gina Sprint, Daniel Iparraguire, and Steve Wang for their camaraderie during my final year. I also want to thank students in EECS for their friendship and help: Vic Valgenti, Tao Yang, Sou Sarkar, Sujay Deb, Turbo Majumder, Ding Ma, Xinmin Yu, Kevin Chang, Tao Yang, Kylan Robinson, and Guillermo Ramirez-Conejo. I especially thank Lorie Mochel for her support, motivation, and assistance during my time at WSU. I also want to thank many other friends and students for their help and friendship during my time at WSU for both my B.S. and Ph.D. I wish to extend a special thank you to my parents, Ray and Donna, my brother Steve, and my relatives for their love, support, and encouragement throughout my life; I could not have been successful in my educational pursuits without this support. I also wish to thank my girlfriend Elizabeth Edwards for her love, support, encouragement, and providing more balance to my life. iii DESIGN TECHNIQUES AND TRADEOFFS OF FINFET SRAM MEMORIES Abstract by Michael Allen Turi, Ph.D. Washington State University May 2013 Chair: José G. Delgado-Frias Nine novel eight-transistor (8T) FinFET SRAM cell schemes using different shorted gate (SG) or low power (LP) FinFET configurations are studied and evaluated comprehensively in terms of leakage current, delay, read and write energy dissipation, energy delay product (EDP), and static noise margin. Comparisons to conventional 6T SRAM schemes reveal that the 8T SRAM schemes perform better, especially for a 32-bit by 1024-word (32×1024) array, since leakage current can be reduced by low-power schemes that reverse-bias the inverter transistors’ back gates without adversely impacting read speed or read static noise margin. FinFETs provide significantly lower leakage current and higher on-current than bulk-CMOS transistors and allow the 8T FinFET SRAM schemes to greatly outperform 8T 32 nm CMOS SRAM cells. 8T SRAM configuration choices further affect these performance metrics. Reverse-biasing the inverter FinFETs’ back gates can reduce leakage current by 2-97%. Additionally, FinFET SRAM cells designed for low-leakage are more effective than header and/or footer transistors added to a cell to reduce leakage current. For a 32×1024 array, read delay is dominant and can be minimized by using SG configuration for the read transistors. These two performance metrics are chiefly responsible for determining the energy consumption of a SRAM array. Reverse-biasing the iv inverter FinFETs’ back gates also minimizes leakage current and EDP variation due to parameter, voltage, and temperature (PVT) variations. The 8T LP_INV, low-power inverters, scheme uses these configurations and is the best-performing FinFET SRAM scheme at a 1 V V , and in particular the 8T LP_INV1.2 cell has 60% less EDP than the conventional 8T SG DD FinFET SRAM scheme and performs best under PVT variations. Similar relative performance is observed for the cells at 0.6 V near-threshold operation; most cells yield reduced EDP and the 8T LP_INV1.2 cell still performs best. However, these cells suffer increased changes in performance due to PVT variations and increased delay. The LP_INV1.2 cell is also the best- performing FinFET SRAM cell at near-threshold operation; however, the 8T LP_SGR cell has less performance variation for PVT variations. The tradeoff is that the LP_SGR cell has a slightly higher average EDP than the LP_INV1.2 cell. v Table of Contents Acknowledgements ...................................................................................................................... iii Abstract ......................................................................................................................................... iv List of Tables ............................................................................................................................... xii List of Figures ............................................................................................................................. xvi Chapter 1 Introduction................................................................................................................. 1 1.1 FinFET Technology ......................................................................................................... 2 1.1.1 FinFET Back-Gate Biasing Strategies ...................................................................... 2 1.1.2 FinFET Technology Model....................................................................................... 4 1.1.3 Simulation Environment ......................................................................................... 14 1.2 SRAM Memories ........................................................................................................... 14 Chapter 2 A Background into 6T SRAM Cells ........................................................................ 16 2.1 6T FinFET SRAM Design Options ................................................................................ 17 2.2 6T FinFET SRAM Design Schemes .............................................................................. 18 2.3 Simulation Setup ............................................................................................................ 19 2.4 6T FinFET SRAM Performance Results ....................................................................... 19 2.4.1 6T FinFET SRAM Dynamic Performance ............................................................. 21 2.4.2 6T FinFET SRAM Leakage Current....................................................................... 22 2.4.3 6T FinFET SRAM Noise Margins .......................................................................... 27 2.4.4 6T FinFET SRAM Overall Performance Summary ............................................... 28 vi Chapter 3 8T SRAM Cells ......................................................................................................... 29 3.1 8T FinFET SRAM Design Options ................................................................................ 29 3.2 8T FinFET SRAM Design Schemes .............................................................................. 32 3.3 Simulation Setup ............................................................................................................ 33 3.4 8T FinFET SRAM Performance Results ....................................................................... 33 3.4.1 8T FinFET SRAM Read Operation ........................................................................ 35 3.4.2 8T FinFET SRAM Write Operation ....................................................................... 37 3.4.3 8T FinFET SRAM Leakage Current....................................................................... 39 33.4.3.1 Cross-Coupled Inverter Leakage .................................................................... 43 33.4.3.2 Write Leakage ................................................................................................. 44 33.4.3.3 Read Leakage .................................................................................................. 46 3.4.4 8T FinFET SRAM Noise Margins .......................................................................... 48 3.4.5 8T FinFET SRAM Overall Performance Summary ............................................... 49 3.5 8T FinFET SRAM Comparisons to 6T FinFET and 8T CMOS .................................... 50 3.5.1 Dynamic Performance Comparisons to 6T FinFET Cells ...................................... 50 3.5.2 Dynamic Performance Comparisons to 32 nm CMOS 8T Cell .............................. 51 3.5.3 Leakage Current Comparisons to 6T FinFET Cells ............................................... 51 3.5.4 Leakage Current Comparisons to 32 nm CMOS 8T Cell ....................................... 52 3.5.5 Noise Margin Comparisons to 6T FinFET Cells .................................................... 53 3.5.6 Noise Margin Comparisons to 32 nm CMOS 8T Cell ............................................ 53 vii Chapter 4 FinFET SRAM under Process Voltage Temperature Variations ........................ 54 4.1 Performance under Process/Parameter Variations ......................................................... 54 4.1.1 Read Operation ....................................................................................................... 56 4.1.2 Write Operation ...................................................................................................... 56 4.1.3 Leakage Current ...................................................................................................... 58 4.1.4 Noise Margins ......................................................................................................... 59 4.1.5 Overall Performance ............................................................................................... 60 4.2 Performance under Supply Voltage Variations .............................................................. 62 4.3 Performance under Bias Voltage Variations .................................................................. 67 4.4 Performance under Temperature Variations .................................................................. 72 4.5 Summary of FinFET SRAM PVT Variations ................................................................ 78 Chapter 5 FinFET SRAM Low-Leakage Modifications ......................................................... 79 5.1 Header/Footer FinFETs per Cell .................................................................................... 80 5.2 Header/Footer FinFETs per Two Cells .......................................................................... 83 5.3 Header/Footer FinFETs per Four Cells .......................................................................... 85 5.4 Summary of SRAM Usage of Header/Footer FinFETs ................................................. 86 Chapter 6 Near-Threshold FinFET SRAM Operation ........................................................... 88 6.1 SRAM Performance Results .......................................................................................... 90 6.2 SRAM Speed Enhancements ....................................................................................... 102 6.2.1 Word-line Boosting for 6T SRAMs ...................................................................... 104 viii 6.2.2 Word-line/Write-line and Read-line Boosting for 8T SRAMs ............................. 106 6.3 Process, Voltage, and Temperature Variations ............................................................ 108 6.3.1 Process/Parameter Variations ............................................................................... 109 6.3.2 Supply Voltage Variations .................................................................................... 113 6.3.3 Bias Voltage Variations ........................................................................................ 118 6.3.4 Temperature Variations ........................................................................................ 123 6.3.5 Summary of PVT Variations ................................................................................ 128 6.4 Low-Leakage Modifications: Header/Footer FinFETs ................................................ 129 Chapter 7 Conclusions .............................................................................................................. 135 7.1 Contributions ................................................................................................................ 138 7.2 Future Work ................................................................................................................. 140 References .................................................................................................................................. 142 Appendix A Simulation Scripts .......................................................................................... 147 A.1 run_ufdg.pl ................................................................................................................... 147 A.2 netgen_ufdg.pl .............................................................................................................. 152 A.3 mkout_ufdg.pl .............................................................................................................. 158 A.4 init_batch_ufdg.pl ........................................................................................................ 163 A.5 batchexec_ufdg.pl ........................................................................................................ 184 A.6 meas_ezwave.pl............................................................................................................ 189 A.7 meas_stub.tcl ................................................................................................................ 196 ix