Design of a 3GSPS ADC board for the iBOB by Michael Carl Gorven Submitted to the Department of Electrical Engineering in partial fulfillment of the requirements for the degree of Bachelor of Science in Electrical and Computer Engineering at the University of Cape Town October 2007 Supervisor: Professor M.R. Inggs Abstract This thesis describes the design, implementation, production and testing ofa3GSPSADCboardfortheiBOBreconfigurablehardwareplatform. The ADC board was developed for use in the KAT project. The design phase consisted of generating a high level, block diagram of the system and then creating the detailed circuit diagram, which was implemented in the PCB layout. Firmware for the iBOB was also developed to support the ADC board. Following the successful completion of the design phase the board was sent to be manufactured. This took longer than expected, which delayed the remainder of the project. The board was populated and some basic tests were conducted. Due to problems with the manufacture of the board and the time con- straints, thorough testing of the board did not take place. However, a testing plan for the system was developed and a list of possible improvements has been included. Declaration Ideclarethatthisdissertationismyown,unaidedwork. Itisbeingsubmitted for the degree of Master of Science in Engineering at the University of Cape Town. It has not been submitted before for any degree or examination at any other university. Michael Gorven Cape Town 22 October 2007 i Contents Declaration i List of Figures vii List of Tables ix Glossary x Acknowledgements xvi 1 Introduction 1 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 CASPER and iBOB . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Project Requirements . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 Requirements Review . . . . . . . . . . . . . . . . . . . . . . . 3 1.5 Project Overview . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5.1 Technical Research . . . . . . . . . . . . . . . . . . . . 4 1.5.2 System Design . . . . . . . . . . . . . . . . . . . . . . 5 1.5.3 Integration and Testing . . . . . . . . . . . . . . . . . . 7 1.5.4 Conclusions and Future Work . . . . . . . . . . . . . . 8 2 Technical Research 10 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 National Semiconductor ADC083000 . . . . . . . . . . 11 2.2.2 e2v EV8AQ160 . . . . . . . . . . . . . . . . . . . . . . 12 ii 2.3 Sampling Clock . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 Phase Noise and Jitter . . . . . . . . . . . . . . . . . . 13 2.3.2 Clock Requirements . . . . . . . . . . . . . . . . . . . 14 2.3.3 National Semiconductor LMX2531 . . . . . . . . . . . 15 2.4 Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.1 Single to Differential Conversion . . . . . . . . . . . . . 17 2.4.2 Mini-Circuits TC1-1-13M . . . . . . . . . . . . . . . . 21 2.5 Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . 21 2.5.1 Maxim MAX6627 . . . . . . . . . . . . . . . . . . . . . 22 2.6 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.6.1 Z-DOK Connector . . . . . . . . . . . . . . . . . . . . 23 2.6.2 SMA Edge Connector . . . . . . . . . . . . . . . . . . 23 2.7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.7.1 Texas Instruments TPS74401 . . . . . . . . . . . . . . 25 2.7.2 Decoupling Capacitors . . . . . . . . . . . . . . . . . . 26 2.8 Level Converters . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8.1 Texas Instruments SN74AUC34 . . . . . . . . . . . . . 26 2.8.2 Texas Instruments SN74LVC2G07 . . . . . . . . . . . . 27 2.9 PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.9.1 Form Factor . . . . . . . . . . . . . . . . . . . . . . . . 27 2.9.2 Manufacturer Capabilities . . . . . . . . . . . . . . . . 27 2.9.3 Impedance Matching . . . . . . . . . . . . . . . . . . . 29 2.9.4 Substrate Material . . . . . . . . . . . . . . . . . . . . 29 2.9.5 Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.9.6 Length Matching . . . . . . . . . . . . . . . . . . . . . 31 2.10 iBOB Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.10.1 iBOB Hardware . . . . . . . . . . . . . . . . . . . . . . 32 2.10.2 Development Kit . . . . . . . . . . . . . . . . . . . . . 32 2.10.3 Firmware Requirements . . . . . . . . . . . . . . . . . 32 2.10.4 Sampled Data . . . . . . . . . . . . . . . . . . . . . . . 33 2.10.5 Serial Interface . . . . . . . . . . . . . . . . . . . . . . 33 2.10.6 Control Lines . . . . . . . . . . . . . . . . . . . . . . . 34 2.11 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . 34 iii 2.11.1 Signal to Noise Ratio . . . . . . . . . . . . . . . . . . . 35 2.11.2 Total Harmonic Distortion . . . . . . . . . . . . . . . . 35 2.11.3 Signal to Noise And Distortion . . . . . . . . . . . . . 35 2.11.4 Effective Number of Bits . . . . . . . . . . . . . . . . . 36 2.11.5 Spurious Free Dynamic Range . . . . . . . . . . . . . . 36 2.12 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3 System Design 38 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2 High Level Design . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.1 Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.2 Input Power . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.4 Level Converters . . . . . . . . . . . . . . . . . . . . . 42 3.3.5 Frequency Synthesiser . . . . . . . . . . . . . . . . . . 43 3.3.6 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.7 Temperature Monitor . . . . . . . . . . . . . . . . . . . 43 3.3.8 Decoupling Capacitors . . . . . . . . . . . . . . . . . . 43 3.3.9 Schematic Capture . . . . . . . . . . . . . . . . . . . . 44 3.4 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4.1 Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4.2 Impedance Matching . . . . . . . . . . . . . . . . . . . 45 3.4.3 Design Rules . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.4 Placement and Planes . . . . . . . . . . . . . . . . . . 46 3.4.5 Decoupling Capacitors . . . . . . . . . . . . . . . . . . 46 3.4.6 ADC Outputs . . . . . . . . . . . . . . . . . . . . . . . 47 3.4.7 Other Traces . . . . . . . . . . . . . . . . . . . . . . . 47 3.5 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.5.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.5.2 Impedance Matching . . . . . . . . . . . . . . . . . . . 48 3.5.3 Signal Integrity . . . . . . . . . . . . . . . . . . . . . . 48 3.6 Preparing for Production . . . . . . . . . . . . . . . . . . . . . 51 iv 3.6.1 Silkscreen . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.6.2 Design Rule Checks . . . . . . . . . . . . . . . . . . . . 51 3.6.3 Gerber Generation . . . . . . . . . . . . . . . . . . . . 51 3.7 Firmware Design . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.7.1 Sampled Data . . . . . . . . . . . . . . . . . . . . . . . 52 3.7.2 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.7.3 Serial Interface . . . . . . . . . . . . . . . . . . . . . . 53 3.7.4 Initialisation . . . . . . . . . . . . . . . . . . . . . . . . 55 3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 Integration and Testing 57 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2 Manufacture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2.1 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3 Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4 Population . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.5 Board Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.5.1 Visual Inspection . . . . . . . . . . . . . . . . . . . . . 64 4.5.2 Form Factor Test . . . . . . . . . . . . . . . . . . . . . 64 4.5.3 DC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.5.4 Power Supplies . . . . . . . . . . . . . . . . . . . . . . 64 4.6 System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.6.1 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.6.2 Frequency Synthesiser . . . . . . . . . . . . . . . . . . 67 4.6.3 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.6.4 External Sampling Clock . . . . . . . . . . . . . . . . . 68 4.6.5 Data Collection . . . . . . . . . . . . . . . . . . . . . . 68 4.6.6 System Test . . . . . . . . . . . . . . . . . . . . . . . . 68 4.7 Performance Testing . . . . . . . . . . . . . . . . . . . . . . . 69 4.7.1 Data Collection . . . . . . . . . . . . . . . . . . . . . . 69 4.7.2 Data Analysis . . . . . . . . . . . . . . . . . . . . . . . 69 4.8 Design Changes . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 v 5 Conclusions and Future Work 73 5.1 Outcomes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3.1 Completion of Integration and Testing . . . . . . . . . 75 5.3.2 Board Revision . . . . . . . . . . . . . . . . . . . . . . 75 5.3.3 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3.4 Interleaving 2 ADC Boards . . . . . . . . . . . . . . . 76 5.3.5 Adapting for ROACH . . . . . . . . . . . . . . . . . . 77 References 78 A Schematic 81 B Board Layout 89 C Firmware Source Code 94 D Simulations 99 vi List of Figures 1.1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Frequencyspectrumofanon-idealoscillatorshowingmeasure- ment of phase noise . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Aperture uncertainty causes an error in the sampled voltage . 14 2.3 LMX2531 Connection Diagram . . . . . . . . . . . . . . . . . 16 √ 2.4 Direct conversion using a 1: 2 transformer . . . . . . . . . . . 18 2.5 Conversion using a 1:1 transformer . . . . . . . . . . . . . . . 18 2.6 Conversion using a 1:1 transformer with double secondary . . 19 2.7 Conversion using a 1:1 transformer with twisted cable . . . . . 20 2.8 Conversion using a 1:1 twisted pair transformer . . . . . . . . 20 2.9 MAX6627 Typical Operating Circuit . . . . . . . . . . . . . . 22 2.10 Z-DOK Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.11 SMA Edge Connector . . . . . . . . . . . . . . . . . . . . . . . 24 2.12 TPS74401 Typical Application Circuit . . . . . . . . . . . . . 25 2.13 Outline, mounting holes and Z-DOK connector on iADC board 28 2.14 Graph of dielectric constant vs frequency for RO4003 and FR-4 30 2.15 Standard stackup for four layer PCBs . . . . . . . . . . . . . . 30 2.16 Non-standard stackup used for the board . . . . . . . . . . . . 31 3.1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . 40 3.2 Final stackup used for the board . . . . . . . . . . . . . . . . . 45 3.3 Simulation of ADC outputs . . . . . . . . . . . . . . . . . . . 49 3.4 Simulation of ADC outputs showing crosstalk . . . . . . . . . 50 4.1 Manufactured PCB . . . . . . . . . . . . . . . . . . . . . . . . 59 vii 4.2 Simulation of ADC outputs on FR-4 material . . . . . . . . . 61 4.3 Simulation of ADC outputs on FR-4 material showing crosstalk 62 4.4 Populated ADC board . . . . . . . . . . . . . . . . . . . . . . 63 4.5 ADC board connected to the iBOB . . . . . . . . . . . . . . . 65 4.6 Plot of 1.9V power supply . . . . . . . . . . . . . . . . . . . . 66 B.1 Top Layer (Assembly) . . . . . . . . . . . . . . . . . . . . . . 90 B.2 Bottom Layer (Assembly) . . . . . . . . . . . . . . . . . . . . 91 B.3 Top Layer (Copper) . . . . . . . . . . . . . . . . . . . . . . . . 92 B.4 Bottom Layer (Copper) . . . . . . . . . . . . . . . . . . . . . . 93 D.1 Simulation of ADC outputs . . . . . . . . . . . . . . . . . . . 100 D.2 Simulation of ADC outputs showing crosstalk . . . . . . . . . 101 viii