THÈSE Pour obtenir le grade de DOCTEUR DE L’UNIVERSITÉ GRENOBLE ALPES préparée dans le cadre d’une cotutelle entre l’Université Grenoble Alpes et l’Université de Pavia Spécialité : Nano Électronique et Nano Technologies et Microélectronique Arrêté ministériel : le 6 janvier 2005 - 7 août 2006 Présentée par Athanasios KIOUSELOGLOU Thèse dirigée par Fabien CLERMIDY et codirigée par Guido TORELLI préparée au sein du CEA-LETI dans l’École Doctorale Électronique, Electrotechnique, Automatique et Traitement du Signal (UGA) et au sein du Laboratoire des Microsystèmes Intégreés du Dipartimento di Ingegneria Industriale e dell’Informazione dans l’École Doctorale de Sciences de l’Ingenierie (UniPV) Caractérisation et conception d’architectures basées sur des mémoires à changement de phase Thèse soutenue publiquement le 17 décembre 2015 devant le jury composé de : Monsieur Jean-Michel PORTAL Prof., Université d'Aix-Marseille (France) Président rapporteur Monsieur Alessandro SPINELLI Prof., Politecnico di Milano (Italie) Rapporteur Monsieur Alessandro CABRINI Ing., Université de Pavia (Italie) Encadrant Monsieur Fabien CLERMIDY HDR, CEA-LETI, Grenoble (France) Directeur de thèse Monsieur Luca PERNIOLA Ing., CEA-LETI, Grenoble (France) Encadrant Monsieur Guido TORELLI Prof., Université de Pavia (Italie) Co-Directeur de thèse Monsieur Jean-Michel MIRABEL Ing., STMicroelectronics, Rousset (France) Invité Contents Contents i Abstract - RØsumØ iii Acknowledgements v Introduction 1 1 Solid-State Memory Technologies 5 1.1 Solid-State Memories - An Overview . . . . . . . . . . . . . . . . . . 7 1.1.1 Static Random Access Memory - SRAM . . . . . . . . . . . . 11 1.1.2 Dynamic Random Access Memory - DRAM . . . . . . . . . . 12 1.1.3 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1.4 Magnetoresistive Random Access Memory - MRAM . . . . . 19 1.1.5 Ferroelectric Random Access Memory - FeRAM . . . . . . . . 21 1.1.6 Resistive Random Access Memory - ReRAM . . . . . . . . . 23 1.2 Phase Change Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.2.1 Historical Background . . . . . . . . . . . . . . . . . . . . . . 27 1.2.2 Phase Change Materials . . . . . . . . . . . . . . . . . . . . . 28 1.2.3 Operation Principle . . . . . . . . . . . . . . . . . . . . . . . 31 1.2.4 The Crystalline Phase . . . . . . . . . . . . . . . . . . . . . . 33 1.2.5 The Amorphous Phase . . . . . . . . . . . . . . . . . . . . . . 35 1.2.6 Phase Change Memory Cell Architectures . . . . . . . . . . . 40 1.2.7 PCM Applications and Challenges . . . . . . . . . . . . . . . 44 1.3 Summary of the Chapter . . . . . . . . . . . . . . . . . . . . . . . . . 52 2 Performance Optimization of Phase Change Memory 55 2.1 Electrical Characterization of the PCM Cell . . . . . . . . . . . . . . 56 2.1.1 Main Electrical Parameters . . . . . . . . . . . . . . . . . . . 56 2.1.2 Thermal Parameters . . . . . . . . . . . . . . . . . . . . . . . 58 2.1.3 The Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.1.4 The Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.2 Phase Change Memory Reliability . . . . . . . . . . . . . . . . . . . 63 2.2.1 Cycling Endurance . . . . . . . . . . . . . . . . . . . . . . . . 65 2.2.2 Data Disturbs . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2.3 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.2.4 Resistance Drift. . . . . . . . . . . . . . . . . . . . . . . . . . 68 ii Contents 2.3 Phase Change Material Engineering . . . . . . . . . . . . . . . . . . 69 2.3.1 N-doped GST . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.3.2 C-doped GST . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.3.3 Ge-rich GST . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.4.1 Thermal Stability . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.4.2 Drift of the Low Resistance State . . . . . . . . . . . . . . . . 82 2.4.3 Crystallization Speed . . . . . . . . . . . . . . . . . . . . . . . 85 2.5 The R(cid:21)SET Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.6 Summary of the Chapter . . . . . . . . . . . . . . . . . . . . . . . . . 91 3 Innovative PCM Circuit Design 93 3.1 The R-SET Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . 94 3.1.1 Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.2 Pulse Generator for Optimized Temperature Pro(cid:28)le . . . . . . . . . . 103 3.2.1 Voltage Controlled Temperature . . . . . . . . . . . . . . . . 103 3.2.2 On-Chip Implementation Design . . . . . . . . . . . . . . . . 104 3.3 Multilevel Cell Programming Circuit . . . . . . . . . . . . . . . . . . 111 3.3.1 MLC Programming Algorithm . . . . . . . . . . . . . . . . . 111 3.3.2 Proposed Pulse Generator . . . . . . . . . . . . . . . . . . . . 115 3.3.3 Programmed Resistance Variation . . . . . . . . . . . . . . . 117 3.4 Summary of the Chapter . . . . . . . . . . . . . . . . . . . . . . . . . 118 4 On-Wafer Pulse Generator 121 4.1 Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.2 Post-Layout Simulations . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.2.1 Schematic vs. Post-Layout Simulations . . . . . . . . . . . . . 137 4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.4 Summary of the Chapter . . . . . . . . . . . . . . . . . . . . . . . . . 145 Conclusions and Perspectives 147 Author’s Publications List 151 Bibliography 153 RØsumØ en fran(cid:231)ais 167 Abstract iii Abstract - RØsumØ Title: Characterization and Design of Architectures for Phase-Change Memories based on alternative-to-GST materials Abstract: Semiconductor memory has always been an indispensable component of modern electronic systems. The increasing demand for highly scaled memory devices has led to the development of reliable non-volatile memories that are used in computing systems for permanent data storage and are capable of achieving high data rates, with the same or lower power dissipation levels as those of current advanced memory solutions. Among the emerging non-volatile memory technologies, Phase Change Memory (PCM) is the most promising candidate to replace conventional Flash memory tech- nology. PCM o(cid:27)ers a wide variety of features, such as fast read and write access, excellent scalability potential, baseline CMOS compatibility and exceptional high- temperature data retention and endurance performances, and can therefore pave the way for applications not only in memory devices, but also in energy demanding, high-performance computer systems. However, some reliability issues still need to be addressed in order for PCM to establish itself as a competitive Flash memory replacement. This work focuses on the study of embedded Phase Change Memory in order to optimize device performance and propose solutions to overcome the key bottlenecks of the technology, targeting high-temperature applications. In order to enhance the reliability of the technology, the stoichiometry of the phase change material was ap- propriately engineered and dopants were added, resulting in an optimized thermal stability of the device. A decrease in the programming speed of the memory tech- nology was also reported, along with a residual resistivity drift of the low resistance state towards higher resistance values over time. A novel programming technique was introduced, thanks to which the program- ming speed of the devices was improved and, at the same time, the resistance drift phenomenon could be successfully addressed. Moreover, an algorithm for program- ming PCM devices to multiple bits per cell using a single-pulse procedure was also presented. A pulse generator dedicated to provide the desired voltage pulses at its output was designed and experimentally tested, (cid:28)tting the programming demands of a wide variety of materials under study and enabling accurate programming tar- geting the performance optimization of the technology. iv RØsumØ Titre: CaractØrisation et conception d’ architectures basØes sur des mØ- moires (cid:224) changement de phase RØsumØ: Les mØmoires (cid:224) base de semi-conducteur sont indispensables pour les dis- positifs Ølectroniques actuels. La demande croissante pour des dispositifs mØmoires fortement miniaturisØs a entra(cid:238)nØ le dØveloppement de mØmoires non volatiles (cid:28)- ables qui sont utilisØes dans des systŁmes informatiques pour le stockage de donnØes et qui sont capables d’atteindre des dØbits de donnØes ØlevØs, avec des niveaux de dissipation d’Ønergie Øquivalents voire moindres que ceux des technologies mØmoires actuelles. Parmi les technologies de mØmoires non-volatiles Ømergentes, les mØmoires (cid:224) changement de phase (PCM) sont le candidat le plus prometteur pour remplacer la technologie de mØmoire Flash conventionnelle. Les PCM o(cid:27)rent une grande variØtØ de fonctions, comme une lecture et une Øcriture rapide, un excellent potentiel de miniaturisation, une compatibilitØ CMOS et des performances ØlevØes de rØtention de donnØes (cid:224) haute tempØrature et d’endurance, et peuvent donc ouvrir la voie (cid:224) des applications non seulement pour les dispositifs mØmoires, mais Øgalement pour les systŁmes informatiques (cid:224) hautes performances. Cependant, certains problŁmes de (cid:28)abilitØ doivent encore Œtre rØsolus pour que les PCM se positionnent comme un remplacement concurrentiel de la mØmoire Flash. Ce travail se concentre sur l’Øtude de mØmoires (cid:224) changement de phase intØgrØes a(cid:28)n d’optimiser leurs performances et de proposer des solutions pour surmonter les principaux points critiques de la technologie, ciblant des applications (cid:224) hautes tempØratures. A(cid:28)n d’amØliorer la (cid:28)abilitØ de la technologie, la st(cid:247)chiomØtrie du matØriau (cid:224) changement de phase a ØtØ con(cid:231)ue de fa(cid:231)on appropriØe et des dopants ontØtØajoutØs, optimisantainsilastabilitØthermique. Unediminutiondelavitesse deprogrammationestØgalementrapportØe,ainsiqu’undriftrØsidueldelarØsistance de l’Øtat faiblement rØsistif vers des valeurs de rØsistance plus ØlevØes au cours du temps. Unenouvelletechniquedeprogrammationestintroduite,permettantd’amØliorer la vitesse de programmation des dispositifs et, dans le mŒme temps, de rØduire avec succŁs le phØnomŁne de drift en rØsistance. Par ailleurs, un algorithme de program- mationdesPCMmulti-bitsestprØsentØ. UngØnØrateurd’impulsionsfournissantdes impulsionsaveclatensionsouhaitØeensortieaØtØcon(cid:231)uettestØexpØrimentalement, rØpondantauxdemandesdeprogrammationd’unegrandevariØtØdematØriauxinno- vants et en permettant la programmation prØcise et l’optimisation des performances des PCM. Acknowledgements First of all, I would like to thank my supervisor Luca Perniola for giving me the opportunity to work in CEA-LETI for the past three years. Having his trust and con(cid:28)dence pushed me and motivated me to work hard and thanks to him, I got the opportunity to work in a great scienti(cid:28)c environment, on a topic that I ended up loving. This period was one of the best of my life, making me better on a personal and a professional level, and this would have not been possible without him putting his trust in me. Iwouldalsoliketothankmythesisdirectors,FabienClermidyandGuidoTorelli for their collaboration and their scienti(cid:28)c input. Alessandro Cabrini, my tutor during my stay in Pavia, is another person I am feeling grateful towards, as well as Olivier Thomas, who guided me during my short collaboration with the memory design team of DACLE. Besides my o(cid:30)cial supervisors, the biggest (cid:16)thank you(cid:17) should be given to my behind-the-scenes supervisor, dear friend and colleague, Gabriele Navarro. I’d like to thank him for always standing next to me, not only professionally, but also personally. Always eager to help me and encourage me for the best, he transmitted his warmth and passion for what he was doing, and I am truly grateful I got to work by his side, learn so many things from him and get to know him on a personal level. Of course I also need to thank my friends for their support and the great times we had together. The old ones, Thilo and Natalija, who I was super lucky to end up working together with and are practically family to me, but also a bunch of new ones, I met in Grenoble and in Pavia, such as CØcile, Daniele, Davide, Erika, Giorgio, Hadi, (besto(cid:30)cemateIcouldeverimagine)Julia, Lorenzo, Marinela, Sara and of course my beloved friend Yiota! Thank you all for stoically listening to my complaints and for always putting a smile on my face! There are also so many colleagues I would like to thank for their collaboration, so hoping that I am not forgetting anyone, I would like to thank Martin, my fellow PCM traveler since day one, Onofrio, Quentin, ThØrŁse, Thomas, Sarra, Boubacar, Adam D., Issam, Vincent, Loic, Alexia, Bastien, Adam M., Alex, Giuseppe, JØrØmy, Mouhamad and Mourad for our great talks and fun times. I would also like to thank my colleagues from the electrical characterization lab, the people from the memory design team in DACLE, and the permanent stu(cid:27) fromthememorycomponentslaboratoryfortheircollaborationandtheirimmediate availability every time I had questions. Last but not least, I would like to thank my colleagues and the professors in the University in Pavia, who also gave me valuable input when I needed help during my stay there. Finally,Iwouldliketothankmyfamilyfortheirunconditionalloveandsupport. Η Ιθάκη σ’ έδωσε τ’ ωραίο ταξίδι, χωρίς αυτην δεν θα ΄βγαινες στον δρόμο. ΄Αλλα δεν έχει να σε δώσει πια. Κι αν πτωχική την βρεις, η Ιθάκη δε σε γέλασε. ΄Ετσι σοφός που έγινες, με τόση πείρα, ήδη θα το κατάλαβες οι Ιθάκες τι σημαίνουν. Ithaca, C. P. Cavafy (1910) Introduction Context Social scientists have reached the conclusion that we are living through an era in which (cid:16)the generation of wealth, the exercise of power, and the creation of cultural codescametodependonthetechnologicalcapacityofsocietiesandindividuals,with information technologies as the core of this capacity(cid:17) [1]. The way modern society handles information, strongly depends on the technological breakthroughs, which allowed us to process and store more information much faster than a few years ago. The information revolution was made possible thanks to several technological improvements in fabrication techniques from one side and to the increased under- standing of solid-state electronics mechanisms from the other side. The invention of the integrated circuit by J. Kilby in 1958 totally changed the world and the way we live on it, while the ability to place a large number of electronic devices on the same chip further allowed for the invention of the (cid:28)rst personal computer in 1977. It was only a matter of time before the Internet became a free platform, gradually connecting all personal computers in the World Wide Web. The exponential technological development of integrated circuits followed the well-knownMoore’slaw, whichwasfairlysimpleinitsconcept: accordingtoMoore, the number of devices that can be integrated on a chip of (cid:28)xed area would double every 12 months. This simple prediction (later amended to doubling the number of devices every 18 - 24 months) unleashed a powerful economic cycle of investment followed by enhanced products and innovative applications motivating even more investment. Moore’s Law has become a driving force behind dramatic reductions in unit cost over the past few decades for memory, enabling products of higher density and ultimately putting enormous amounts of memory in the hands of the consumer at reduced cost [2]. Semiconductor memory has always been an indispensable component of modern electronic systems. All familiar computing platforms, ranging from hand-held de- vices to large supercomputers, use storage systems for storing data temporarily or permanently, having reached TB of capacities in considerably less space and power consumption, yet maintaining a high speed [3]. The roots of memory technologies used in modern computing systems date back toearly1970’s,whenthesemiconductorindustrywasstillinitsnascentstage. These technologies include solid-state memories such as Static RAM (SRAM), Dynamic RAM (DRAM), and EPROM, as well as mechanical memories like tape and Hard Disk Drive (HDD). 2 Introduction From (cid:29)oppy disks and magnetic Hard Disk Drives to Flash memory cards and Solid-State Drives conventionally used nowadays, there has been a remarkable increase in the available memory capacity during the past years, enabling higher storage density at a lower price. The scalability of these memory technologies has been a key factor in the emer- gence of increasingly complex computing devices, however, the exponentially in- creasing demand for an enriched end-user experience and increased performance in mainstream computing applications is rendering these memory technologies ob- solete. Driven by multi-core computing, virtualization, and processor integration trends, the global electronics and semiconductor industry has been feeling the need for next-generation main memory solutions that are capable of achieving high data rates, with the same or lower power dissipation levels as that of current advanced conventional memory solutions. For non-volatile data storage, magnetic hard disk drives have been in use for over (cid:28)ve decades. Nonetheless, since the arrival of portable electronic devices such as music players and mobile phones, Flash memory has been introduced into the information storage hierarchy between DRAM and HDD. Flash has become the dominant data storage device for mobile electronics. Even enterprise-scale comput- ing systems and cloud data storage systems use Flash to complement the storage capabilities of HDD. Nevertheless, the integration limit of Flash memories is slowly approaching, and many new types of memory have been proposed to replace con- ventional Flash technology. Emerging non-volatile memory technologies such as magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive random access memory (ReRAM) and phase change memory (PCM) combine the speed of SRAM, the density of DRAM, and the non-volatility of Flash and therefore, are continuously being investigated since they demonstrate characteristics which are very attractive for future memory hierarchies [4]. PCM is considered the leading solution for the next NVM generation, demon- strating numerous advantages that make it competitive against established memory technologies, not only for stand-alone, but for embedded applications as well, and showinguniquecapabilitieswithrespecttocompetingmemorytechnologies. Thanks to its proven good scalability as well as easy integration in advanced CMOS nodes, high-density memory demonstrators and even commercial products have made their