BBrriigghhaamm YYoouunngg UUnniivveerrssiittyy BBYYUU SScchhoollaarrssAArrcchhiivvee Theses and Dissertations 2004-04-29 DDeessiiggnn aanndd AAnnaallyyssiiss ooff CChhaarrggee--TTrraannssffeerr AAmmpplliififieerrss ffoorr LLooww--PPoowweerr AAnnaalloogg--ttoo--DDiiggiittaall CCoonnvveerrtteerr AApppplliiccaattiioonnss William Joel Marble Brigham Young University - Provo Follow this and additional works at: https://scholarsarchive.byu.edu/etd Part of the Electrical and Computer Engineering Commons BBYYUU SScchhoollaarrssAArrcchhiivvee CCiittaattiioonn Marble, William Joel, "Design and Analysis of Charge-Transfer Amplifiers for Low-Power Analog-to-Digital Converter Applications" (2004). Theses and Dissertations. 35. https://scholarsarchive.byu.edu/etd/35 This Dissertation is brought to you for free and open access by BYU ScholarsArchive. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of BYU ScholarsArchive. For more information, please contact [email protected], [email protected]. DESIGN AND ANALYSIS OF CHARGE-TRANSFER AMPLIFIERS FOR LOW-POWER ANALOG-TO-DIGITAL CONVERTER APPLICATIONS by William J. Marble A dissertation submitted to the faculty of Brigham Young University in partial ful(cid:12)llment of the requirements for the degree of Doctor of Philosophy Department of Electrical and Computer Engineering Brigham Young University August 2004 Copyright c 2004 William J. Marble (cid:13) All Rights Reserved BRIGHAM YOUNG UNIVERSITY GRADUATE COMMITTEE APPROVAL of a dissertation submitted by William J. Marble This dissertation has been read by each member of the following graduate committee and by majority vote has been found to be satisfactory. Date Craig S. Petrie, Chair Date Donald T. Comer Date David J. Comer Date Brian D. Je(cid:11)s Date Mark L. Manwaring BRIGHAM YOUNG UNIVERSITY As chair of the candidate’s graduate committee, I have read the dissertation of William J. Marble in its (cid:12)nal form and have found that (1) its format, citations, and bibliographical style are consistent and acceptable and ful(cid:12)ll university and de- partment style requirements; (2) its illustrative materials including (cid:12)gures, tables, and charts are in place; and (3) the (cid:12)nal manuscript is satisfactory to the graduate committee and is ready for submission to the university library. Date Craig S. Petrie Chair, Graduate Committee Accepted for the Department Michael A. Jensen Graduate Coordinator Accepted for the College Douglas M. Chabries Dean, College of Engineering and Technology ABSTRACT DESIGN AND ANALYSIS OF CHARGE-TRANSFER AMPLIFIERS FOR LOW-POWER ANALOG-TO-DIGITAL CONVERTER APPLICATIONS William J. Marble Electrical and Computer Engineering Doctor of Philosophy The demand for low-power A/D conversion techniques has motivated the exploration of charge-transfer ampli(cid:12)ers (CTAs) to construct eÆcient, precise voltage comparators. Despite notable advantages over classical, continuous-time architec- tures, little is understood about the dynamic behavior of CTAs or their utility in precision A/D converters. Accordingly, this dissertation presents several advance- ments related to the design and analysis of charge-transfer ampli(cid:12)ers for low-power data conversion. First, an analysis methodology is proposed which leads to a deterministic modelofthe voltagetransfer function. The modelisgeneralizedtoany timingscheme and can be extended to account for nonlinear threshold modulation. The model is compared with simulation results and test chip measurements, and shows good agreement over a broad range of circuit parameters. Three new charge-transfer ampli(cid:12)er architectures are proposed to address the limitationsofexisting designs: (cid:12)rst, atrulydi(cid:11)erentialCTA which improvesupon the pseudo-di(cid:11)erential con(cid:12)guration; second, a CTA which achieves more than 10x reduction in input capacitance with a moderate reduction in common mode range; third, a CTA which combines elements of the (cid:12)rst two but also operates without a precharge voltage and achieves nearly rail to rail input range. Results from test chips fabricated in 0.6 (cid:22)m CMOS are described. Power dissipation in CTAs is considered and an idealized power consump- tion modelis compared withmeasured test chipresults. Four(cid:12)gures ofmerit(FOMs) are also proposed, incorporatingpower dissipation, active area, input charging energy and accuracy. The FOMs are used to compare the relative bene(cid:12)ts and costs of par- ticular charge-transfer ampli(cid:12)ers with respect to (cid:13)ash A/D converter applications. The (cid:12)rst 10-bit CTA-based A/D converter is reported. It consumes low dynamicpower of600 (cid:22)W/MSPS froma2.1V supply, 40% lessthan thecurrent state of the art of 1 mW/MSPS. This subranging type converter incorporates capacitive interpolation to achieve a nearly ideal comparator count and power consumption. A distributed sample-and-hold (S/H) eliminates the need for a separate S/H ampli(cid:12)er. 2 A test chip, fabricated in 0.6 (cid:22)m 2P/3M CMOS, occupies 2.7 mm and exhibits 8.2 e(cid:11)ective bits at 2 MSPS. ACKNOWLEDGMENTS Iwish toexpress mysincere appreciationtomyresearch advisor, Dr. Craig Petrie, for his guidance and support during this e(cid:11)ort. It has been a great pleasure to learn from him during the process of expanding and re(cid:12)ning my research. He has been a generous mentor and a good friend. IalsowanttothankDr. DonComerforthemanyvaluablediscussionsearly oninmygraduateresearch. Hisencouragementtotakerisks, coupledwithhis incisive understanding of circuit techniques, was instrumental in creating an environment in which I was able to embrace this research topic and eventually experience many exciting opportunities to work on the cutting edge of low-power circuit design. This work would not have been possible without the commitment of AMI Semiconductor. I owe a special thanks to the managers who enthusiastically sup- ported me: Ryan Cameron, Jerry Downey and Robert Klosterboer. One of the most in(cid:13)uential forces on the course of this research has been Dr. KojiKotani,whoseoriginalworksparkedmyinterestincharge-transferampli(cid:12)ers (cid:12)ve years ago. Though we have never met, our many email discussions have greatly enriched my graduate studies. I am truly grateful for his perspectives and ideas and hope we will be able to collaborate further in the future. My deepest thanks go to my parents for their encouragement in all of my endeavors. Arguably, my interest in power-eÆcient circuits was motivated at a young age by their countless sermons on conservation and frugality. They have been a primary source of inspiration and teaching throughout my life. Finally,IexpressmysinceregratitudetomydearwifeRoseforherconstant support and patience throughout this e(cid:11)ort. To Rosemary Contents Acknowledgments vii Dedication viii List of Tables xiii List of Figures xviii 1 Abbreviations and Conventions 1 2 Introduction 3 2.1 A Brief History of Charge-transfer Ampli(cid:12)ers . . . . . . . . . . . . . 4 2.1.1 Transconveyance . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Low-power A/D Converters . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 A/D Converter Speci(cid:12)cations . . . . . . . . . . . . . . . . . . 9 2.2.2 Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Contributions of this Work . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 Organization of the Dissertation . . . . . . . . . . . . . . . . . . . . . 19 3 Existing CTA Architectures 21 3.1 NMOS Charge-transfer Ampli(cid:12)er . . . . . . . . . . . . . . . . . . . . 21 3.2 CMOS Charge-transfer Ampli(cid:12)er . . . . . . . . . . . . . . . . . . . . 24 3.3 Pseudo-di(cid:11)erential Charge-transfer Ampli(cid:12)er . . . . . . . . . . . . . . 25 3.4 Feedback Charge-transfer Ampli(cid:12)er . . . . . . . . . . . . . . . . . . . 25 4 Analysis of Dynamic Behavior 29 4.1 Analysis of the NMOS Charge-transfer Ampli(cid:12)er . . . . . . . . . . . 29 ix