CMOS VLSI ENGINEERING Silicon-on-Insulator (SOl) CMOS VLSI ENGINEERING Silicon-on-Insulator (SOl) by JAMESB.KUO and KER-WEI SU National Taiwan University Springer-Science+Business Media, B.Y. Library of Congress Cataloging-in-Publication Data ISBN 978-1-4419-5057-4 ISBN 978-1-4757-2823-1 (eBook) DOI 10.1007/978-1-4757-2823-1 Printed on acid-free paper All Rights Reserved © 1998 Springer Science+Business Media Dordrecht Originally published by Kluwer Academic Publishers in 1998. Softcover reprint of the hardcover 1s t edition 1998 No part of the material protected by this copyright notice may be reproduced or utilized in any fonn or by any means, electronic or mechanical, including photocopying, recording or by any infonnation storage and retrieval system, without written pennission from the copyright owner. Acknow ledgements The authors would like to thanks colleagues in Taiwan and professors at Stanford for their support during the past 11 years. Without their encouragements, this work is not possible. The author would like to thank J. H. Lou, S. C. Lin, C. H. Hsu, C. K. Huang, C. Y. Huang, Y. M. Huang, J. Y. Lai, R. J. Liu, J. C. Su, H. K. Sui, and K. H. Yuan, for their help on drawing. The author would like to thank Ms. Cindy Lufting, Mr. James Finlay, and Mr. Mike Casey of Kluwer for their help such that this book could be published. Preface Silicon-On-Insulator (SOl) CMOS VLSI technology has been regarded as another major technology for VLSI in addition to bulk CMOS technology. Owing to the buried oxide isolation structure, SOl technology offers superior CMOS devices with higher speed, higher density, and reduced second order effects for deep-submicron low-voltage, low-power VLSI circuit applications. In addition to VLSI applications, SOl technology has also been used to realize communication circuits, microwave devices, BiCMOS devices, and even fiber optics applications for its superior prop erties. There are three key factors in engineering SOl CMOS VLSI- processing technology, device modeling, and circuit designs. The mutual influences from three factors are important in developing a creative SOl CMOS VLSI technology. Im provements in the processing technology and understanding of the device behaviors lead to progresses in the SOl circuit designs. Requirements for low-voltage low power high-performance SOl circuits in the world-wide portable systems serve as an incentive to further evolve the SOl CMOS processing technology. Understanding of the SOl CMOS device behaviors can provide new ideas for development of the next-generation SOl CMOS technology. In addition, the developed SOl CMOS de vice models can provide CAD tools for circuit simulation. In this book, these three key factors in engineering SOl CMOS VLSI are covered. Starting from the SOl CMOS processing technology and the SOl CMOS digital and analog circuits, be haviors of the SOl CMOS devices are presented. In addition, a CAD program-ST SPICE, which incorporates models for deep-submicron fully-depleted mesa-isolated SOl CMOS devices, is described. This book is written for undergraduate senior stu dents and first-year graduate students interested in CMOS VLSI. The arrangement of the book is designed for a 3 semester-unit course. This book is also suitable for electrical engineering professionals interested in microelectronics. James B. Kuo and Ker-Wei Su Taipei, Taiwan November 1998 III About the Authors Prof. James B. Kuo received BSEE from National Taiwan University in 1977, MSEE from Ohio State University in 1978, and PhDEE from Stanford University in 1985. Since 1987, he has been with National Taiwan University, and currently is a pro fessor. He has published numerous international journal papers. He serves as an associate editor for the IEEE Circuits and Devices Magazine and an AdCom mem ber for the IEEE Electron Devices Society. Dr. Ker-Wei Su received BSEE and PhDEE from National Taiwan University in 1994 and 1998, respectively. His research specialty is modeling of SOl CMOS de vices. v Contents 1 Introduction 1 1.1 What is SOl? 1 1.2 Objectives . . 9 2 SOl CMOS Technology 15 2.1 Evolution of SOl ... 15 2.2 SIMOX SOl Substrate 17 2.3 Other SOl Substrates . 26 2.3.1 SOS Substrate. 26 2.3.2 ZMR SOl Substrate 27 2.3.3 BESOI Substrate . . 31 2.3.4 Smart-Cut SOl Technology 36 2.4 Isolation Technology ........ 38 2.5 0.25p,m SOl CMOS Processing Sequence 43 2.6 SOl CMOS Structures .......... 50 2.6.1 Accumulation-mode versus Inversion-mode 50 2.6.2 Partially Depleted versus Fully Depleted 52 2.6.3 Double Gate & DELTA 55 2.6.4 Quasi-SOl ......... 59 2.7 Special-purpose SOl Technologies 60 2.7.1 SOl DRAM. 60 2.7.2 SOl BiCMOS 62 2.7.3 SOl Power. 65 2.8 Summary ..... 66 3 SOl CMOS Circuits 71 3.1 Floating Body Effects . 71 3.2 Low-Voltage SOl Circuits 75 3.3 SOl Gate Arrays ..... 81 vii vIn CONTENTS 3.4 SOl SRAM 87 3.5 SOl DRAM 92 3.6 SOl CPU · 103 3.7 SOl Analog Circuits · 106 3.8 Summary · 115 4 SOl CMOS Devices-Basic 121 4.1 Back Gate Bias Effect · 122 4.1.1 NMOS device · 123 4.1.2 PMOS device · 126 4.2 Short-Channel Effect · 131 4.3 Narrow-Channel Effect · 143 4.4 Three-Dimensional effect · 150 4.5 Mobility .. · 158 4.5.1 Surface scattering mobility. · 158 4.5.2 Electron temperature. · 160 4.6 Subthreshold Current . . · 162 4.6.1 Center portion .. · 166 4.6.2 Sidewall portion .... · 169 4.7 Strong Inversion Drain Current · 173 4.7.1 Triode region (VD < VDSAT) · 175 4.7.2 Saturation region (VD > VDSAT) · 177 4.8 Source/Drain Resistance Effects · 185 4.9 Impact Ionization · 188 4.10 Non-Local Effect · 194 4.11 Summary .... · 198 5 SOl CMOS Devices-Advanced 207 5.1 Accumulation-mode - Drain Current · 208 5.1.1 Mobile Carriers · 212 5.1.2 Drain current ..... . · 214 5.2 Capacitance Model . . . · 223 5.3 Capacitance Model: Accumulation-Mode Devices · 228 5.4 Capacitance Model: Inversion-Mode Devices · 238 5.5 Sensitivity. . ..... . · 242 5.6 Floating Body Effects(I) ..... . · 244 5.6.1 Triode Region (VDS :::; VDSAT) . . · 250 5.6.2 Saturation Region (VDS > VDSAT) · 251 5.7 Floating Body Effects(II) . · 255 CONTENTS ix 5.8 Transient Analysis .263 5.9 Hot Carrier Effects .270 5.10 Thermal Analysis . · 278 5.11 Radiation Hardness. .287 5.12 Noise ... · 290 5.13 Summary ..... . · 295 6 SOl-Technology ST-SPICE 307 6.1 Overview.......... . 307 6.2 BSIM Models . . . . . . . . 308 6.3 Threshold Voltage Model. . 312 6.4 Subthreshold Current Model. . 315 6.5 Mobility and Strong-Inversion Current Model . 316 6.5.1 Triode Region . . . . 316 6.5.2 Saturation Region. . 317 6.6 Capacitance Model . . . . 321 6.6.1 triode region. . . . . 321 6.6.2 saturation region . . 324 6.6.3 fringing capacitance. . 325 6.7 Non-Local Impact Ionization & Parasitic BJT Effects Model . 325 6.8 Thermal Effect Model .... . 326 6.9 Usage of ST-SPICE . . . . . . . 327 6.9.1 Steady State Analysis . 329 6.9.2 Transient Analysis .. . 333 6.10 Implications from ST-SPICE . . 338 6.11 Summary . . . . . . . . . . . . 338 7 Special-Purpose SOl 345 7.1 Fully-Depleted Lean-Channel Transistors (DELTA) .345 7.2 SiGe SOl PMOS Devices . · 351 7.3 SOl Power Devices ... · 356 7.4 SOl BJT & BiCMOS . . . .363 7.5 SOl MESFET & JFET .. .370 7.6 Single-Electron Transistor(SET) .372 7.7 Amorphous TFT . . . . . .375 7.8 Polysilicon TFT ..... . .382 7.8.1 Moderate Inversion .389 7.8.2 Strong Inversion .. .398 7.8.3 Capacitance Model .403 x CONTENTS 7.9 Summary ................................. 406