Vaibbhav Taraate ASIC Design and Synthesis RTL Design Using Verilog ASIC Design and Synthesis Vaibbhav Taraate ASIC Design and Synthesis RTL Design Using Verilog 123 Vaibbhav Taraate 1 RupeeST Pune,Maharashtra, India ISBN978-981-33-4641-3 ISBN978-981-33-4642-0 (eBook) https://doi.org/10.1007/978-981-33-4642-0 ©SpringerNatureSingaporePteLtd.2021 Thisworkissubjecttocopyright.AllrightsarereservedbythePublisher,whetherthewholeorpart of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission orinformationstorageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilar methodologynowknownorhereafterdeveloped. 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The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore Dedicated to my inspiration and my friend who wish to create many entrepreneurs in VLSI design Late Ajit Shelat Ajit unfortunately passed away on 1st September 2010 in car accident. Due to wish of Ajit I have continued work in ASIC and VLSI design. Preface The complexity of the ASIC designs has grown exponentially during the past decade, and during this decade, we areexperiencing theAI/ML-based designs and AI-based processor cores to improve the performance of the designs. The book is the origin of my thought process, and I have tried to document the design concepts and practical issues with their solutions in this book. The book mainly covers the ASIC design concepts, semi-custom ASIC design flow and the case studies which can be helpful to the postgraduates and profes- sionals.ThebookusestheSynopsysDCandPTcommandsandtheiruseduringthe synthesis and timing closure. The physical design flow with the basic steps are covered so that readers can have better understanding about the overall ASIC design cycle. The bookisorganised in20chaptersandcovers thebasicsofASIC designand the concepts used during the RTL design to GDSII flow. Chapter 1: Introduction: Understanding of the ASIC and programmable ASIC plays an important role for the beginners and the experience engineers. The flow can be full-custom, semi-custom, or programmable ASIC, and the major objective ofanengineeristounderstandthedesignstepstoplanthemilestonedelivery.The objective of this chapter is to have the basic understanding of ASICs and what should be the focus of the design team. Chapter 2: ASIC Design Flow: The chapter discusses about the ASIC design flow with few oftheexamples. Thechapterisuseful tounderstand about thelogic design (frontend design) flow, physical design (backend design) flow and the design flow for the programmable ASICs. Chapter 3: Let Us Build Design Foundation: Understanding of the design abstraction at various levels is always useful during the RTL design and synthesis phase.Inthiscontext,thechapterdiscussesaboutfewoftheelementsandtheiruse during the design. Even the chapter discusses about the area improvement tech- niques and role of the design elements in the ASIC design. vii viii Preface Chapter4:SequentialDesignConcepts:Theobjectiveofthischapteristohave discussion on the synchronous sequential circuits and asynchronous designs and their use during the design phase. For better understanding, the chapter discusses about the sequential elements and their use during design cycle. Chapter 5: Important Design Considerations: The chapter is useful to under- stand about the basics of timing, skew, latency, and other design considerations such as parallelism and concurrency. Chapter 6: Important Considerations for ASIC Designs: The chapter dis- cusses about these techniques which are useful during the ASIC design architec- tures and micro-architectures. Chapter 7: Multiple Clock Domain Designs: The chapter discusses about the multiple clock domain designs and strategies which can be useful during the architecture and micro-architecture design. Chapter 8: Low Power Design Considerations: The chapter is useful to understand about the low power design techniques and important strategies which are useful during the ASIC design. Chapter 9: Architecture and Micro-architecture Design: The chapter dis- cusses about the architecture and micro-architecture design concepts and strategies which can be useful during the ASIC design phase. Chapter 10: Design Constraints and SDC Commands: The chapter discusses aboutthedesign constraintsandtheimportantSDCcommands.SDCstandsforthe SynopsysDesignConstraints whichisformatandusedtospecifythedesignintent, including timing, power and area constraints for a design!. Chapter 11: Design Synthesis and Optimization Using RTL Tweaks: The chapter discusses about the ASIC and FPGA synthesis and important concepts useful during the design optimization ad even during RTL design phase. Chapter 12: Synthesis and Optimization Techniques: The chapter is useful to understand the different optimization techniques used during logic synthesis and use of Synopsys DC commands while optimizing the design. Chapter 13: Design Optimization and Scenarios: The chapter discusses about the optimization for the speed and area with the practical design scenarios. Chapter 14: Design for Testability: The DFT and the testability basics for the ASIC design are discussed in this chapter. Chapter 15: Timing Analysis: The STA and the performance improvement techniques are discussed in this chapter. Chapter 16: Physical Design: The chapter discusses about the physical design flow and important issues during the physical design and how to overcome them. Chapter 17: Case Study: Processor ASIC Implementation: The chapter dis- cusses about the overall strategies which are useful during RTL to GDSII for the moderately complex processors. Even thechapterdiscusses about the performance improvement and the processor architecture strategies with and without pipelining stages. Chapter 18: Programmable ASIC: The FPGA and the role in prototyping is discussedinthischapter. EventhechapterisusefultounderstandabouttheFPGA flow and the FPGA synthesis. Preface ix Chapter 19: Prototyping Design: The design prototyping and the strategies are discussed in this chapter. The use of multi-FPGA architecture, use of the multiple FPGAs during prototyping and the prototyping flow is also discussed in this chapter! Chapter 20: Case Study: IP Design and Development: The IP development and the strategies are discussed in this chapter. The H.264 architecture design and strategies to implement the design is also included in this chapter! The book is useful to understand the ASIC design flow and the important design concepts useful during the various phases from the architecture design to layout of the chip. Pune, India Vaibbhav Taraate Acknowledgements The book is originated due to my extensive work in FPGA and ASIC design from year2000.Thejourneytodevelopthealgorithmsandarchitectureswillcontinuein future also and will be helpful to many professionals and engineers. This book is possible due to help of many people. I am thankful to all the participants to whom I taught the subject FPGA and ASIC design, synthesis, and timing closure in few multinational corporations. I am thankful to all those entre- preneurs, design/verification engineers, and managers with whom I worked in the past almost around 20 years. I am thankful to all my dearest friends and well-wishers for their constant support.Especially,Iamthankfultomyteammates andallmyfamilymembers for theirsupportandcooperation!.ThankfultoNirajandDeepeshfortheir supportand cooperation during the manuscript completion phase! Finally, I am thankful to Springer Nature staff, especially Swati Meherishi, AshokKumar,RiniChristy,andJayaranifortheirgreatsupportduringthevarious phases of the manuscript. Special thanks in advance to all the readers and engineers for buying, reading, and enjoying this book! xi Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 ASIC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Types of ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Abstraction Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 What We Should Know?. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6 Important Terms Used Throughout Design Cycle . . . . . . . . . . 11 1.7 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 ASIC Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 ASIC Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.1 Logic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.2 Physical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 FPGA Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 Examples and Thought Process . . . . . . . . . . . . . . . . . . . . . . . 24 2.4 Design Challenges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 Let Us Build Design Foundation. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.1 Combinational Design Elements. . . . . . . . . . . . . . . . . . . . . . . 27 3.2 Logic Understanding and Use of Construct. . . . . . . . . . . . . . . 28 3.3 Arithmetic Resources and Area . . . . . . . . . . . . . . . . . . . . . . . 29 3.4 Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.1 Binary to Gray Code Converter. . . . . . . . . . . . . . . . . 31 3.4.2 Gray to Binary Code Converter. . . . . . . . . . . . . . . . . 33 3.5 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6 Cascading Stages of MUX Using Instantiation . . . . . . . . . . . . 38 3.7 Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.8 Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.9 Priority Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 xiii