Applications Development on the ARM® Cortex™-M0+ Free On-line Development Tools Presented by William Antunes 2 Agenda – Cortex M0+ architecture – Introduction to Kinetis L – Freedom board – Arrow Cloud Connect – Internet of Things introduction – iDigi cloud services overview – First IoT application – Customer dashboard development 3 ARM® Cortex™-M0+ Reasons to migrate to 32-bit core? • “I need more performance.” • “I need more connectivity” • “I need more memory” Reasons not to migrate to 32-bit core? • “I need low power” • “I need low cost” The Cortex-M0+ was designed to provide all the benefits of a 32-bit core at 8-bit/16-bit power and cost. ARM® Cortex™ M0+ 5 ARM® Cortex™-M0+ Bus Architecture 6 ARM® Cortex™-M0+ Low Latency I/O Interface I/O Interface provides “Harvard- like” access to peripherals Improves overall cycle efficiency for I/O access 7 ARM® Cortex™-M0+ Performance ARM7 Cortex-M4 Cortex-M0 Cortex-M0+ Pipeline 3 3 3 2 Bus Arch. Von Neumann Harvard Von Neumann Von Neumann ISA Arm/Thumb Thumb-2 Thumb(wT2) Thumb(wT2) DMIPS/MHz 0.95/0.70 1.25 0.84 0.93 MPU No Optional No Optional Interrupts 2 1 - 240 1-32 1-32 Area 0.34 mm2 0.17 mm2 0.04 mm2 0.04 mm2 Power 70µW/MHz 33 µW/MHz 16 µW/MHz 11 µW/MHz 8 ARM® Cortex™-M0+ So what does this really mean for 8 and 16-bit cores? 9 ARM Cortex-M0+ Memory Map 32-bit registers means 4GB address space No paging, swapping, or instruction set extensions common in 8 & 16 bit architectures 10 ARM Cortex-M0+ Instruction Efficiency 32-bit means instruction set efficiency This means better memory usage and fewer clock cycles