ARM Arch PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Thu, 31 Jul 2014 12:40:42 UTC Contents ARM architecture 1 List of ARM microarchitectures 19 ARM7 22 ARM9 26 ARM11 30 ARM Cortex-A 37 XScale 39 Comparison of ARMv7-A cores 44 References Article Sources and Contributors 46 Image Sources, Licenses and Contributors 47 Article Licenses License 48 ARM architecture 1 ARM architecture ARM architectures The ARM logo Designer ARM Holdings Bits 32-bit, 64-bit Introduced 1985 Design RISC Type Register-Register Branching Condition code Open Proprietary 64/32-bit architecture Introduced 2011 Version ARMv8-A Encoding AArch64/A64 and AArch32/A32 use 32-bit instructions, T32 (Thumb-2) uses mixed 16- and 32-bit instructions. ARMv7 user-space compatibility Endianness Bi (little as default) Extensions All mandatory: Thumb-2, NEON, Jazelle, VFPv4-D16, VFPv4 Registers General 31x 64-bit integer registers plus PC and SP, ELR, SPSR for exception levels purpose Floating point 32× 128-bit registers, scalar 32- and 64-bit FP, SIMD 64- and 128-bit FP and integer 32-bit architectures (Cortex) Version ARMv8-R, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-M Encoding 32-bit except Thumb-2 extensions use mixed 16- and 32-bit instructions. Endianness Bi (little as default) Extensions Thumb-2 (mandatory since ARMv7), NEON, Jazelle, FPv4-SP Registers General purpose 16x 32-bit integer registers including PC and SP Floating point Up to 32× 64-bit registers, SIMD/floating-point (optional) ARM architecture 2 32-bit architectures (legacy) Version ARMv6, ARMv5, ARMv4T, ARMv3, ARMv2 Encoding 32-bit except Thumb extension uses mixed 16- and 32-bit instructions. Endianness Bi (little as default) in ARMv3 and above Extensions Thumb, Jazelle Registers General purpose 16x 32-bit integer registers including PC (26-bit addressing in older) and SP ARM is a family of instruction set architectures for computer processors based on a reduced instruction set computing (RISC) architecture developed by British company ARM Holdings. A RISC-based computer design approach means ARM processors require significantly fewer transistors than typical CISC x86 processors in most personal computers. This approach reduces costs, heat and power use. These are desirable traits for light, portable, battery-powered devices— including smartphones, laptops, tablet and notepad computers, and other embedded systems. A simpler design facilitates more efficient multi-core CPUs and higher [1][2][3] core counts at lower cost, providing improved energy efficiency for servers. ARM Holdings develops the instruction set and architecture for ARM-based products, but does not manufacture products. The company periodically releases updates to its cores. Current cores from ARM Holdings support a 32-bit address space and 32-bit arithmetic; the ARMv8-A architecture, announced in October 2011, adds support for a 64-bit address space and 64-bit arithmetic. Instructions for ARM Holdings' cores have 32 bits wide fixed-length instructions, but later versions of the architecture also support a variable-length instruction set that provides both 32 and 16 bits wide instructions for improved code density. Some cores can also provide hardware execution of Java bytecodes. ARM Holdings licenses the chip designs and the ARM instruction set architectures to third parties, who design their own products that implement one of those architectures— including systems-on-chips (SoC) that incorporate memory, interfaces, radios, etc. Currently, the widely used Cortex cores, older "classic" cores, and specialized SecurCore cores variants are available for each of these to include or exclude optional capabilities. Companies that make chips that implement an ARM architecture include Apple, Nvidia, Qualcomm, Samsung Electronics, and Texas Instruments. Globally ARM is the most widely used instruction set architecture in terms of quantity produced. The low power consumption of ARM processors has made them very popular: over 50 billion ARM processors have been produced as of 2014[4], thereof 10 billion in 2013 and "ARM-based chips are found in nearly 60 percent of the world’s mobile devices". In 2008, 10 billion chips had been produced. The ARM architecture (32-bit) is the most widely used architecture in mobile devices, and most popular 32-bit one in embedded systems. In 2005, about 98% of all mobile phones sold used at least one ARM processor. According to ARM Holdings, in 2010 alone, producers of chips based on ARM architectures reported shipments of 6.1 billion ARM-based processors, representing 95% of smartphones, 35% of digital televisions and set-top boxes and 10% of mobile computers. ARM architecture 3 History The British computer manufacturer Acorn Computers first developed ARM in the 1980s to use in its personal computers. Its first ARM-based products were coprocessor modules for the BBC Micro series of computers. After the successful BBC Micro computer, Acorn Computers considered how to move on from the relatively simple MOS Technology 6502 processor to address business markets like the one that was soon dominated by the IBM PC, launched in 1981. The Acorn Business Computer (ABC) plan required that a number of second processors be made to work with the BBC Micro platform, but processors such as the Motorola 68000 and National Semiconductor 32016 were considered unsuitable, and the 6502 was not powerful enough for a graphics based user interface. After testing all available processors and finding them lacking, Acorn decided it needed a new architecture. Inspired by white Microprocessor-based system on a chip papers on the Berkeley RISC project, Acorn considered designing its own processor. A visit to the Western Design Center in Phoenix, where the 6502 was being updated by what was effectively a single-person company, showed Acorn engineers Steve Furber and Sophie Wilson they did not need massive resources and state-of-the-art research and development facilities. Wilson developed the instruction set, The ARM1 second processor for the BBC Micro writing a simulation of the processor in BBC BASIC that ran on a BBC Micro with a second 6502 processor. This convinced Acorn engineers they were on the right track. Wilson approached Acorn's CEO, Hermann Hauser, and requested more resources. Once he had approval, he assembled a small team to implement Wilson's model in hardware. Acorn RISC Machine: ARM2 The official Acorn RISC Machine project started in October 1983. They chose VLSI Technology as the silicon partner, as they were a source of ROMs and custom chips for Acorn. Wilson and Furber led the design. They implemented it with a similar efficiency ethos as the 6502. A key design goal was achieving low-latency input/output (interrupt) handling like the 6502. The 6502's memory access architecture had let developers produce fast machines without costly direct memory access hardware. ARM architecture 4 VLSI produced the first ARM silicon on 26 April 1985. It worked the first time, and was known as ARM1 by April 1985. The first production systems named ARM2 were available the following year. The first ARM application was as a second processor for the BBC Micro, where it helped in developing simulation software to finish development of the support chips (VIDC, IOC, MEMC), and sped up the CAD software used in ARM2 development. Wilson subsequently rewrote BBC BASIC in ARM assembly language. The in-depth knowledge gained from designing the instruction set enabled the code to be very dense, making ARM BBC BASIC an extremely good test for any ARM emulator. The original aim of a principally ARM-based computer was achieved in 1987 with the release of the Acorn Archimedes. In 1992, Acorn once more won the Queen's Award for Technology for the ARM. The ARM2 featured a 32-bit data bus, 26-bit address space and 27 32-bit registers. Eight bits from the program counter register were available for other purposes; the top six bits (available because of the 26-bit address space), served as status flags, and the bottom two bits (available because the program counter was always word-aligned), were used for setting modes. The address bus was extended to 32 bits in the ARM6, but program code still had to lie within the first 64 MB of memory in 26-bit compatibility mode, due to the reserved bits for the status flags. The ARM2 had a transistor count of just 30,000, compared to Motorola's six-year-older 68000 model with around 40,000. Much of this simplicity came from the lack of microcode (which represents about one-quarter to one-third of the 68000) and from (like most CPUs of the day) not including any cache. This simplicity enabled low power consumption, yet better performance than the Intel 80286. A successor, ARM3, was produced with a 4 KB cache, which further improved performance. Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScale In the late 1980s Apple Computer and VLSI Technology started working with Acorn on newer versions of the ARM core. In 1990, Acorn spun off the design team into a new company named Acorn RISC Machines Ltd., which became ARM Ltd when its parent company, ARM Holdings plc, floated on the London Stock Exchange [4] and NASDAQ in 1998. The new Apple-ARM work would eventually evolve into the ARM6, first released in early 1992. Apple used the ARM6-based ARM610 as the basis for their Apple Newton PDA. In 1994, Acorn used the ARM610 as the main central processing unit (CPU) in their RiscPC computers. DEC licensed the ARM6 architecture and produced the StrongARM. At 233 MHz, this CPU drew only one watt (newer Die of an ARM610 microprocessor. versions draw far less). This work was later passed to Intel as a part of a lawsuit settlement, and Intel took the opportunity to supplement their i960 line with the StrongARM. Intel later developed its own high performance implementation named XScale, which it has since sold to Marvell. Transistor count of the ARM core remained essentially the same size throughout these changes; ARM2 had 30,000 transistors, while ARM6 grew only to 35,000.Wikipedia:Citation needed ARM architecture 5 Licensing See also: ARM Holdings § Licensees Core license ARM Holdings' primary business is selling IP cores, which licensees use to create microcontrollers (MCUs) and CPUs based on those cores. The original design manufacturer combines the ARM core with other parts to produce a complete CPU, typically one that can be built in existing semiconductor fabs at low cost and still deliver substantial performance. The most successful implementation has been the ARM7TDMI with hundreds of millions sold. Atmel has been a precursor design center in the ARM7TDMI-based embedded system. The ARM architectures used in smartphones, PDAs and other mobile devices range from ARMv5, used in low-end devices, through Die of a STM32F103VGT6 ARM Cortex-M3 ARMv6, to ARMv7 in current high-end devices. ARMv7 includes a microcontroller with 1 megabyte flash memory by STMicroelectronics. hardware floating-point unit (FPU), with improved speed compared to software-based floating-point. In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition with netbooks based on Intel Atom. According to analyst firm IHS iSuppli, by 2015, ARM ICs may be in 23% of all laptops. ARM Holdings offers a variety of licensing terms, varying in cost and deliverables. ARM Holdings provides to all licensees an integratable hardware description of the ARM core as well as complete software development toolset (compiler, debugger, software development kit) and the right to sell manufactured silicon containing the ARM CPU. SoC packages integrating ARM's core designs include Nvidia Tegra's first three generations, CSR plc's Quatro family, ST-Ericsson's Nova and NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's OMAP products, Samsung's Hummingbird and Exynos products, Apple's A4, A5, and A5X, and Freescale's i.MX. Fabless licensees, who wish to integrate an ARM core into their own chip design, are usually only interested in acquiring a ready-to-manufacture verified IP core. For these customers, ARM Holdings delivers a gate netlist description of the chosen ARM core, along with an abstracted simulation model and test programs to aid design integration and verification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators, choose to acquire the processor IP in synthesizable RTL (Verilog) form. With the synthesizable RTL, the customer has the ability to perform architectural level optimisations and extensions. This allows the designer to achieve exotic design goals not otherwise possible with an unmodified netlist (high clock speed, very low power consumption, instruction set extensions, etc.). While ARM Holdings does not grant the licensee the right to resell the ARM architecture itself, licensees may freely sell manufactured product such as chip devices, evaluation boards and complete systems. Merchant foundries can be a special case; not only are they allowed to sell finished silicon containing ARM cores, they generally hold the right to re-manufacture ARM cores for other customers. ARM Holdings prices its IP based on perceived value. Lower performing ARM cores typically have lower licence costs than higher performing cores. In implementation terms, a synthesizable core costs more than a hard macro (blackbox) core. Complicating price matters, a merchant foundry that holds an ARM licence, such as Samsung or Fujitsu, can offer fab customers reduced licensing costs. In exchange for acquiring the ARM core through the foundry's in-house design services, the customer can reduce or eliminate payment of ARM's upfront licence fee. Compared to dedicated semiconductor foundries (such as TSMC and UMC) without in-house design services, Fujitsu/Samsung charge two- to three-times more per manufactured wafer.Wikipedia:Citation needed For low to mid ARM architecture 6 volume applications, a design service foundry offers lower overall pricing (through subsidisation of the licence fee). For high volume mass-produced parts, the long term cost reduction achievable through lower wafer pricing reduces the impact of ARM's NRE (Non-Recurring Engineering) costs, making the dedicated foundry a better choice. Architectural licence Companies can also obtain an ARM architectural licence for designing their own CPU cores using the ARM instruction sets. These cores must comply fully with the ARM architecture. Cores Main article: List of ARM cores Architecture Bit Cores designed by ARM Holdings Cores designed by third Cortex profile References width parties ARMv1 32/26 ARM1 ARMv2 32/26 ARM2, ARM3 Amber, STORM Open Soft Core ARMv3 32 ARM6, ARM7 ARMv4 32 ARM8 StrongARM, FA526 ARMv4T 32 ARM7TDMI, ARM9TDMI ARMv5 32 ARM7EJ, ARM9E, ARM10E XScale, FA626TE, Feroceon, PJ1/Mohawk ARMv6 32 ARM11 ARMv6-M 32 ARM Cortex-M0, ARM Cortex-M0+, ARM Cortex-M1 Microcontroller ARMv7-M 32 ARM Cortex-M3 Microcontroller ARMv7E-M 32 ARM Cortex-M4 Microcontroller ARMv7-R 32 ARM Cortex-R4, ARM Cortex-R5, ARM Cortex-R7 Real-time ARMv7-A 32 ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-A8, ARM Krait, Scorpion, PJ4/Sheeva, Application Cortex-A9, ARM Cortex-A12, ARM Cortex-A15, ARM Apple A6/A6X (Swift) Cortex-A17 ARMv8-A 64/32 ARM Cortex-A53, ARM Cortex-A57 X-Gene, Denver, Apple Application [5][6] A7 (Cyclone), AMD K12 ARMv8-R 32 No announcements yet Real-time [7] A list of vendors who implement ARM cores in their design (application specific standard products (ASSP), microprocessor and microcontrollers) is provided by ARM Holdings. ARM architecture 7 Example applications of ARM cores Main article: List of applications of ARM cores ARM cores are used in a number of products, particularly PDAs and smartphones. Some computing examples are the Microsoft Surface, Apple's iPad and ASUS Eee Pad Transformer. Others include Apple's iPhone smartphone and iPod portable media player, Canon PowerShot A470 digital camera, Nintendo DS handheld game console and TomTom turn-by-turn navigation system. In 2005, ARM Holdings took part in the development of Manchester University's computer, SpiNNaker, which used ARM cores to simulate the human brain. Tronsmart MK908, a Rockchip-based quad-core ARM chips are also used in Raspberry Pi, BeagleBoard, BeagleBone, Android "mini PC", with a microSD card next to it for a size comparison. PandaBoard and other single-board computers, because they are very small, inexpensive and consume very little power. 32-bit architecture The 32-bit ARM architecture, such as ARMv7-A, is the most widely used architecture in mobile devices. [9] From 1995, the ARM Architecture Reference Manual has been the primary source of documentation on the ARM processor architecture and instruction set, distinguishing interfaces that all ARM processors are required to support (such as instruction semantics) from implementation details that may vary. The architecture has evolved over time, and version seven of the architecture, ARMv7, that defines the architecture for the first of the Cortex series of cores, defines three architecture "profiles": • A-profile, the "Application" profile: Cortex-A series • R-profile, the "Real-time" profile: Cortex-R series • M-profile, the "Microcontroller" profile: Cortex-M series Although the architecture profiles were first defined for ARMv7, ARM subsequently defined the ARMv6-M architecture (used by the Cortex M0/M0+/M1) as a subset of the ARMv7-M profile with fewer instructions. CPU modes Except in the M-profile, the 32-bit ARM architecture specifies several CPU modes, depending on the implemented architecture features. At any moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically. • User mode: The only non-privileged mode. • FIQ mode: A privileged mode that is entered whenever the processor accepts an FIQ interrupt. • IRQ mode: A privileged mode that is entered whenever the processor accepts an IRQ interrupt. • Supervisor (svc) mode: A privileged mode entered whenever the CPU is reset or when an SVC instruction is executed. • Abort mode: A privileged mode that is entered whenever a prefetch abort or data abort exception occurs. • Undefined mode: A privileged mode that is entered whenever an undefined instruction exception occurs. • System mode (ARMv4 and above): The only privileged mode that is not entered by an exception. It can only be entered by executing an instruction that explicitly writes to the mode bits of the CPSR. • Monitor mode (ARMv6 and ARMv7 Security Extensions, ARMv8 EL3): A monitor mode is introduced to support TrustZone extension in ARM cores. ARM architecture 8 • Hyp mode (ARMv7 Virtualization Extensions, ARMv8 EL2): A hypervisor mode that supports Popek and Goldberg virtualization requirements for the non-secure operation of the CPU. Instruction set The original (and subsequent) ARM implementation was hardwired without microcode, like the much simpler 8-bit 6502 processor used in prior Acorn microcomputers. The 32-bit ARM architecture (and the 64-bit architecture for the most part) includes the following RISC features: • Load/store architecture. • No support for unaligned memory accesses in the original version of the architecture. ARMv6 and later, except some microcontroller versions, support unaligned accesses for half-word and single-word load/store instructions with some limitations, such as no guaranteed atomicity. • Uniform 16× 32-bit register file (including the Program Counter, Stack Pointer and the Link Register). • Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. Later, the Thumb instruction set added 16-bit instructions and increased code density. •• Mostly single clock-cycle execution. To compensate for the simpler design, compared with processors like the Intel 80286 and Motorola 68020, some additional design features were used: • Conditional execution of most instructions reduces branch overhead and compensates for the lack of a branch predictor. • Arithmetic instructions alter condition codes only when desired. • 32-bit barrel shifter can be used without performance penalty with most arithmetic instructions and address calculations. • Has powerful indexed addressing modes. • A link register supports fast leaf function calls. • A simple, but fast, 2-priority-level interrupt subsystem has switched register banks. Arithmetic instructions The ARM supports add, subtract, and multiply instructions. The integer divide instructions are only implemented by ARM cores based on the following ARM architectures: •• ARMv7-M and ARMv7E-M architectures always include divide instructions. •• ARMv7-R architecture always includes divide instructions in the Thumb instruction set, but optionally in its 32-bit instruction set. •• ARMv7-A architecture optionally includes the divide instructions. The instructions might not be implemented, or implemented only in the Thumb instruction set, or implemented in both the Thumb and ARM instructions sets, or implemented if the Virtualization Extensions are included. Registers